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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-22 00:27:40 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-25 00:59:28 +0900
commit28f40d4a4db2b6c701d349fd4fac286d21369de2 (patch)
tree5e5e2fdf2be0c3226ac782c857eb4e3edefbbf54 /arch/arm/mach-uniphier/debug_ll.S
parent323d1f9d5bebfe55e97e23c8094055685665afef (diff)
downloadtalos-obmc-uboot-28f40d4a4db2b6c701d349fd4fac286d21369de2.tar.gz
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ARM: uniphier: add PH1-Pro5 support
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/debug_ll.S')
-rw-r--r--arch/arm/mach-uniphier/debug_ll.S24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S
index d5ccad3244..056f77ed55 100644
--- a/arch/arm/mach-uniphier/debug_ll.S
+++ b/arch/arm/mach-uniphier/debug_ll.S
@@ -101,6 +101,30 @@ ph1_pro4_end:
b init_uart
ph1_sld8_end:
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+#define PH1_PRO5_UART_CLK 73728000
+ cmp r1, #0x2A
+ bne ph1_pro5_end
+
+ sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
+ sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
+ sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_pro5_end:
+#endif
init_uart:
addruart r0, r1, r2
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