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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-22 00:27:41 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-25 00:59:33 +0900 |
commit | 019df879a93e266ac19f5eb00e4ee605db279b14 (patch) | |
tree | b11ab5f86fa406775d870b1a51b2cf44fc8f7acc /arch/arm/mach-uniphier/debug_ll.S | |
parent | 28f40d4a4db2b6c701d349fd4fac286d21369de2 (diff) | |
download | talos-obmc-uboot-019df879a93e266ac19f5eb00e4ee605db279b14.tar.gz talos-obmc-uboot-019df879a93e266ac19f5eb00e4ee605db279b14.zip |
ARM: uniphier: add ProXstream2 and PH1-LD6b support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/debug_ll.S')
-rw-r--r-- | arch/arm/mach-uniphier/debug_ll.S | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S index 056f77ed55..d8c9fe43e3 100644 --- a/arch/arm/mach-uniphier/debug_ll.S +++ b/arch/arm/mach-uniphier/debug_ll.S @@ -125,6 +125,55 @@ ph1_sld8_end: b init_uart ph1_pro5_end: #endif +#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) +#define PROXSTREAM2_UART_CLK 88900000 + cmp r1, #0x2E + bne proxstream2_end + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0 + sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1 + sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2 + sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3 + + ldr r0, =SC_CLKCTRL + ldr r1, [r0] + orr r1, r1, #SC_CLKCTRL_CEN_PERI + str r1, [r0] + + ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE) + + b init_uart +proxstream2_end: +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) +#define PH1_LD6B_UART_CLK 88900000 + cmp r1, #0x2F + bne ph1_ld6b_end + + ldr r0, =SG_IECTRL + ldr r1, [r0] + orr r1, r1, #1 + str r1, [r0] + + sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0 + sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1 + sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2 + + ldr r0, =SC_CLKCTRL + ldr r1, [r0] + orr r1, r1, #SC_CLKCTRL_CEN_PERI + str r1, [r0] + + ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE) + + b init_uart +ph1_ld6b_end: +#endif init_uart: addruart r0, r1, r2 |