ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 77 insertions, 0 deletions

diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
new file mode 100644
index 0000000000..39024a09d5
--- /dev/null
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <mach/ddrphy-regs.h>
+
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a878400, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+#ifdef CONFIG_DDR_STANDARD
+	writel(0x00000000, &phy->mr3);
+#else
+	writel(0x00000800, &phy->mr3);
+#endif
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+
+	return 0;
+}