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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 14:08:28 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 10:09:00 -0700 |
| commit | f2c60eed513ecc142e0a39373d5c16a14f976d6d (patch) | |
| tree | 55ada1683e0fd84d9d3307c1cd4ebaa80143c73e /arch/arm/mach-tegra | |
| parent | b2cd3d810387095e525522de6cae2716f4c20870 (diff) | |
| download | talos-obmc-uboot-f2c60eed513ecc142e0a39373d5c16a14f976d6d.tar.gz talos-obmc-uboot-f2c60eed513ecc142e0a39373d5c16a14f976d6d.zip | |
ARM: tegra: pinmux: support hsm/schmitt on pins
T210 support HSM and Schmitt options in the pinmux register (previous
chips placed these options in the drive group register). Update the
code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux-common.c | 66 |
1 files changed, 64 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 1730d20312..b4ed153a2e 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -61,12 +61,12 @@ (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) #endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) #define pmux_schmt_isvalid(schmt) \ (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) #endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) #define pmux_hsm_isvalid(hsm) \ (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) #endif @@ -110,7 +110,13 @@ #ifdef CONFIG_TEGRA210 #define IO_SHIFT 6 #define LOCK_SHIFT 7 +#ifdef TEGRA_PMX_PINS_HAVE_HSM +#define HSM_SHIFT 9 +#endif #define OD_SHIFT 11 +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT +#define SCHMT_SHIFT 12 +#endif #else #define IO_SHIFT 5 #define OD_SHIFT 6 @@ -336,6 +342,56 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin, } #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT +static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt) +{ + u32 *reg = REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (schmt == PMUX_SCHMT_NONE) + return; + + /* Error check pad */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_schmt_isvalid(schmt)); + + val = readl(reg); + if (schmt == PMUX_SCHMT_ENABLE) + val |= (1 << SCHMT_SHIFT); + else + val &= ~(1 << SCHMT_SHIFT); + writel(val, reg); + + return; +} +#endif + +#ifdef TEGRA_PMX_PINS_HAVE_HSM +static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm) +{ + u32 *reg = REG(grp); + u32 val; + + /* NONE means unspecified/do not change/use POR value */ + if (hsm == PMUX_HSM_NONE) + return; + + /* Error check pad */ + assert(pmux_pingrp_isvalid(pin)); + assert(pmux_hsm_isvalid(hsm)); + + val = readl(reg); + if (hsm == PMUX_HSM_ENABLE) + val |= (1 << HSM_SHIFT); + else + val &= ~(1 << HSM_SHIFT); + writel(val, reg); + + return; +} +#endif + static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) { enum pmux_pingrp pin = config->pingrp; @@ -358,6 +414,12 @@ static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL pinmux_set_rcv_sel(pin, config->rcv_sel); #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + pinmux_set_schmt(pin, config->schmt); +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + pinmux_set_hsm(pin, config->hsm); +#endif } void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, |
