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| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 11:42:20 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-09-16 16:10:22 -0700 |
| commit | 97c02d87f4b08556a36903ce4c5aa9744a95b91e (patch) | |
| tree | d98ea2074e30e33beb7edf8a067e212c328e5687 /arch/arm/mach-tegra/tegra210/clock.c | |
| parent | c043c0259cd88f39cdca5f98af8b10f178660745 (diff) | |
| download | talos-obmc-uboot-97c02d87f4b08556a36903ce4c5aa9744a95b91e.tar.gz talos-obmc-uboot-97c02d87f4b08556a36903ce4c5aa9744a95b91e.zip | |
ARM: tegra: clk_m is the architected timer source clock
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra210/clock.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra210/clock.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 146bb6453a..6d75d371cb 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1014,13 +1014,11 @@ void arch_timer_init(void) struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; u32 freq, val; - freq = clock_get_rate(CLOCK_ID_OSC); - debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + freq = clock_get_rate(CLOCK_ID_CLK_M); + debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); - /* ARM CNTFRQ */ -#ifndef CONFIG_ARM64 - asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); -#endif + if (current_el() == 3) + asm("msr cntfrq_el0, %0\n" : : "r" (freq)); /* Only Tegra114+ has the System Counter regs */ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); |
