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| author | Simon Glass <sjg@chromium.org> | 2015-08-10 07:14:36 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-13 13:06:04 -0700 |
| commit | 5a30cee5d05f0ef0470b85f94907022704598253 (patch) | |
| tree | c0cf4cf1f57b09c09be1dfd12a543b991a82ce0d /arch/arm/mach-tegra/tegra124 | |
| parent | 35f590f4c3300f1aa6bcd2c69ff2f96839cdd85c (diff) | |
| download | talos-obmc-uboot-5a30cee5d05f0ef0470b85f94907022704598253.tar.gz talos-obmc-uboot-5a30cee5d05f0ef0470b85f94907022704598253.zip | |
tegra: Correct logic for reading pll_misc in clock_start_pll()
The logic for simple PLLs on T124 was broken by this commit:
722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Correct it by reading from the same pll_misc register that it writes to and
adding an entry for the DP PLL in the pllinfo table.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra124')
| -rw-r--r-- | arch/arm/mach-tegra/tegra124/clock.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 912621863a..291b75276c 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -570,7 +570,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { */ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { /* - * T124: same as T114, some deviations from T2x/T30. + * T124: same as T114, some deviations from T2x/T30. Adds PLLDP. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.) * If lock_ena or lock_det are >31, they're not used in that PLL. */ @@ -593,6 +593,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, + .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; /* |
