path: root/arch/arm/mach-tegra/tegra114
diff options
authorThierry Reding <>2015-09-08 11:38:04 +0200
committerTom Warren <>2015-09-16 16:11:31 -0700
commit8e1601d994e2fa8b8c7826470c3d923a684492a4 (patch)
treebe4bc580ea0ce2f4005efbf1f54a5f346e5c8c21 /arch/arm/mach-tegra/tegra114
parentaba11d4476b56eb7712184597eb303ae544f0c69 (diff)
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding <> Signed-off-by: Tom Warren <>
Diffstat (limited to 'arch/arm/mach-tegra/tegra114')
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index cec843b27d..e6ef873c8d 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -629,6 +629,11 @@ void clock_early_init(void)
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
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