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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-07-28 14:16:45 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-12 20:47:53 -0400 |
| commit | 74af583e9f7a255443d8f625c8dce6da7b9703be (patch) | |
| tree | fbd63bb5fad0a796a8dcfcf4cfca0623fa235f17 /arch/arm/mach-keystone/clock.c | |
| parent | 7b50e1599f4e6551a3348ca5f061a596f6f6896e (diff) | |
| download | talos-obmc-uboot-74af583e9f7a255443d8f625c8dce6da7b9703be.tar.gz talos-obmc-uboot-74af583e9f7a255443d8f625c8dce6da7b9703be.zip | |
ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/clock.c')
| -rw-r--r-- | arch/arm/mach-keystone/clock.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index aaeef79bd3..de5dfe15eb 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -25,6 +25,14 @@ int __weak speeds[DEVSPEED_NUMSPDS] = { SPD800, }; +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + static void wait_for_completion(const struct pll_init_data *data) { int i; |
