Merge branch 'master' of git://git.denx.de/u-boot

120 files changed, 239 insertions, 10045 deletions

diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h
deleted file mode 100644
index f2db8e1061..0000000000
--- a/arch/arm/include/asm/arch-a320/a320.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __A320_H
-#define __A320_H
-
-/*
- * Hardware register bases
- */
-#define CONFIG_FTSMC020_BASE	0x90200000	/* Static Memory Controller */
-#define CONFIG_DEBUG_LED	0x902ffffc	/* Debug LED */
-#define CONFIG_FTSDMC020_BASE	0x90300000	/* SDRAM Controller */
-#define CONFIG_FTMAC100_BASE	0x90900000	/* Ethernet */
-#define CONFIG_FTPMU010_BASE	0x98100000	/* Power Management Unit */
-#define CONFIG_FTTMR010_BASE	0x98400000	/* Timer */
-#define CONFIG_FTRTC010_BASE	0x98600000	/* Real Time Clock*/
-
-#endif	/* __A320_H */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index b94b56cba7..523d22eb87 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -400,6 +400,8 @@ struct prm_device_inst {
 struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
+	unsigned int resv2[11];
+	unsigned int clkselmacclk;	/* offset 0x34 */ 
 };
 #endif /* CONFIG_AM43XX */
 
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
deleted file mode 100644
index efcd74ed90..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_COMMON_H
-#define AT91_COMMON_H
-
-void at91_can_hw_init(void);
-void at91_gmac_hw_init(void);
-void at91_macb_hw_init(void);
-void at91_mci_hw_init(void);
-void at91_serial0_hw_init(void);
-void at91_serial1_hw_init(void);
-void at91_serial2_hw_init(void);
-void at91_seriald_hw_init(void);
-void at91_spi0_hw_init(unsigned long cs_mask);
-void at91_spi1_hw_init(unsigned long cs_mask);
-void at91_udp_hw_init(void);
-void at91_uhp_hw_init(void);
-void at91_lcd_hw_init(void);
-void at91_plla_init(u32 pllar);
-void at91_pllb_init(u32 pllar);
-void at91_mck_init(u32 mckr);
-void at91_pmc_init(void);
-void mem_init(void);
-void at91_phy_reset(void);
-void at91_sdram_hw_init(void);
-void at91_mck_init(u32 mckr);
-void at91_spl_board_init(void);
-void at91_disable_wdt(void);
-void matrix_init(void);
-void redirect_int_from_saic_to_aic(void);
-
-#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
deleted file mode 100644
index 7346fc0569..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Debug Unit
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_DBU_H
-#define AT91_DBU_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_dbu {
-	u32	cr;	/* Control Register WO */
-	u32	mr;	/* Mode Register  RW */
-	u32	ier;	/* Interrupt Enable Register WO */
-	u32	idr;	/* Interrupt Disable Register WO */
-	u32	imr;	/* Interrupt Mask Register RO */
-	u32	sr;	/* Status Register RO */
-	u32	rhr;	/* Receive Holding Register RO */
-	u32	thr;	/* Transmit Holding Register WO */
-	u32	brgr;	/* Baud Rate Generator Register RW */
-	u32	res1[7];/* 0x0024 - 0x003C Reserved */
-	u32	cidr;	/* Chip ID Register RO */
-	u32	exid;	/* Chip ID Extension Register RO */
-	u32	fnr;	/* Force NTRST Register RW */
-} at91_dbu_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_DBU_CID_ARCH_MASK		0x0ff00000
-#define AT91_DBU_CID_ARCH_9xx		0x01900000
-#define AT91_DBU_CID_ARCH_9XExx	0x02900000
-
-#define AT91_DBU_CIDR_MASK		0x1f
-#define AT91_DBU_CIDR			0x40
-#define AT91_DBU_EXID			0x44
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h
deleted file mode 100644
index 7ffbaee27d..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_eefc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Enhanced Embedded Flash Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_EEFC_H
-#define AT91_EEFC_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_eefc {
-	u32	fmr;	/* Flash Mode Register RW */
-	u32	fcr;	/* Flash Command Register WO */
-	u32	fsr;	/* Flash Status Register RO */
-	u32	frr;	/* Flash Result Register RO */
-} at91_eefc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_EEFC_FMR_FWS_MASK	0x00000f00
-#define AT91_EEFC_FMR_FRDY_BIT	0x00000001
-
-#define AT91_EEFC_FCR_KEY		0x5a000000
-#define AT91_EEFC_FCR_FARG_MASK	0x00ffff00
-#define AT91_EEFC_FCR_FARG_SHIFT	8
-#define AT91_EEFC_FCR_FCMD_GETD	0x0
-#define AT91_EEFC_FCR_FCMD_WP		0x1
-#define AT91_EEFC_FCR_FCMD_WPL		0x2
-#define AT91_EEFC_FCR_FCMD_EWP		0x3
-#define AT91_EEFC_FCR_FCMD_EWPL	0x4
-#define AT91_EEFC_FCR_FCMD_EA		0x5
-#define AT91_EEFC_FCR_FCMD_SLB		0x8
-#define AT91_EEFC_FCR_FCMD_CLB		0x9
-#define AT91_EEFC_FCR_FCMD_GLB		0xA
-#define AT91_EEFC_FCR_FCMD_SGPB	0xB
-#define AT91_EEFC_FCR_FCMD_CGPB	0xC
-#define AT91_EEFC_FCR_FCMD_GGPB	0xD
-
-#define AT91_EEFC_FSR_FRDY	1
-#define AT91_EEFC_FSR_FCMDE	2
-#define AT91_EEFC_FSR_FLOCKE	4
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/include/asm/arch-at91/at91_emac.h
deleted file mode 100644
index a0d74ab660..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_emac.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_H
-#define AT91_H
-
-typedef struct at91_emac {
-	u32	 ctl;
-	u32	 cfg;
-	u32	 sr;
-	u32	 tar;
-	u32	 tcr;
-	u32	 tsr;
-	u32	 rbqp;
-	u32	 reserved0;
-	u32	 rsr;
-	u32	 isr;
-	u32	 ier;
-	u32	 idr;
-	u32	 imr;
-	u32	 man;
-	u32	 reserved1[2];
-	u32	 fra;
-	u32	 scol;
-	u32	 mocl;
-	u32	 ok;
-	u32	 seqe;
-	u32	 ale;
-	u32	 dte;
-	u32	 lcol;
-	u32	 ecol;
-	u32	 cse;
-	u32	 tue;
-	u32	 cde;
-	u32	 elr;
-	u32	 rjb;
-	u32	 usf;
-	u32	 sqee;
-	u32	 drfc;
-	u32	 reserved2[3];
-	u32	 hsh;
-	u32	 hsl;
-	u32	 sa1l;
-	u32	 sa1h;
-	u32	 sa2l;
-	u32	 sa2h;
-	u32	 sa3l;
-	u32	 sa3h;
-	u32	 sa4l;
-	u32	 sa4h;
-} at91_emac_t;
-
-#define AT91_EMAC_CTL_LB	0x0001
-#define AT91_EMAC_CTL_LBL	0x0002
-#define AT91_EMAC_CTL_RE	0x0004
-#define AT91_EMAC_CTL_TE	0x0008
-#define AT91_EMAC_CTL_MPE	0x0010
-#define AT91_EMAC_CTL_CSR	0x0020
-#define AT91_EMAC_CTL_ISR	0x0040
-#define AT91_EMAC_CTL_WES	0x0080
-#define AT91_EMAC_CTL_BP	0x1000
-
-#define AT91_EMAC_CFG_SPD	0x0001
-#define AT91_EMAC_CFG_FD	0x0002
-#define AT91_EMAC_CFG_BR	0x0004
-#define AT91_EMAC_CFG_CAF	0x0010
-#define AT91_EMAC_CFG_NBC	0x0020
-#define AT91_EMAC_CFG_MTI	0x0040
-#define AT91_EMAC_CFG_UNI	0x0080
-#define AT91_EMAC_CFG_BIG	0x0100
-#define AT91_EMAC_CFG_EAE	0x0200
-#define AT91_EMAC_CFG_CLK_MASK	0xFFFFF3FF
-#define AT91_EMAC_CFG_MCLK_8	0x0000
-#define AT91_EMAC_CFG_MCLK_16	0x0400
-#define AT91_EMAC_CFG_MCLK_32	0x0800
-#define AT91_EMAC_CFG_MCLK_64	0x0C00
-#define AT91_EMAC_CFG_RTY	0x1000
-#define AT91_EMAC_CFG_RMII	0x2000
-
-#define AT91_EMAC_SR_LINK	0x0001
-#define AT91_EMAC_SR_MDIO	0x0002
-#define AT91_EMAC_SR_IDLE	0x0004
-
-#define AT91_EMAC_TCR_LEN(x)	(x & 0x7FF)
-#define AT91_EMAC_TCR_NCRC	0x8000
-
-#define AT91_EMAC_TSR_OVR	0x0001
-#define AT91_EMAC_TSR_COL	0x0002
-#define AT91_EMAC_TSR_RLE	0x0004
-#define AT91_EMAC_TSR_TXIDLE	0x0008
-#define AT91_EMAC_TSR_BNQ	0x0010
-#define AT91_EMAC_TSR_COMP	0x0020
-#define AT91_EMAC_TSR_UND	0x0040
-
-#define AT91_EMAC_RSR_BNA	0x0001
-#define AT91_EMAC_RSR_REC	0x0002
-#define AT91_EMAC_RSR_OVR	0x0004
-
-/*  ISR, IER, IDR, IMR use the same bits */
-#define AT91_EMAC_IxR_DONE	0x0001
-#define AT91_EMAC_IxR_RCOM	0x0002
-#define AT91_EMAC_IxR_RBNA	0x0004
-#define AT91_EMAC_IxR_TOVR	0x0008
-#define AT91_EMAC_IxR_TUND	0x0010
-#define AT91_EMAC_IxR_RTRY	0x0020
-#define AT91_EMAC_IxR_TBRE	0x0040
-#define AT91_EMAC_IxR_TCOM	0x0080
-#define AT91_EMAC_IxR_TIDLE	0x0100
-#define AT91_EMAC_IxR_LINK	0x0200
-#define AT91_EMAC_IxR_ROVR	0x0400
-#define AT91_EMAC_IxR_HRESP	0x0800
-
-#define AT91_EMAC_MAN_DATA_MASK		0xFFFF
-#define AT91_EMAC_MAN_CODE_802_3	0x00020000
-#define AT91_EMAC_MAN_REGA(reg)		((reg & 0x1F) << 18)
-#define AT91_EMAC_MAN_PHYA(phy)		((phy & 0x1F) << 23)
-#define AT91_EMAC_MAN_RW_R		0x20000000
-#define AT91_EMAC_MAN_RW_W		0x10000000
-#define AT91_EMAC_MAN_HIGH		0x40000000
-#define AT91_EMAC_MAN_LOW		0x80000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/include/asm/arch-at91/at91_gpbr.h
deleted file mode 100644
index e781481e88..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_gpbr.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * General Purpose Backup Registers
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_GPBR_H
-#define AT91_GPBR_H
-
-/*
- * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
- * 32 Bit registers (buffered by the Vbu power).
- *
- * Please consider carefully before using this resource for tasks
- * that do not really need nonvolatile registers. Maybe you can
- * store information in EEPROM or FLASH instead.
- *
- * However, if you use a GPBR please document its use here and
- * reference the define in your code!
- *
- * known typical uses of the GPBRs:
- * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
- * GPBR[1]: unused
- * GPBR[2]: unused
- * GPBR[3]: bootcount (u-boot)
- */
-#define AT91_GPBR_INDEX_TIMEOFF 0
-#define AT91_GPBR_INDEX_BOOTCOUNT 3
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_gpbr {
-	u32 reg[4];
-} at91_gpbr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h
deleted file mode 100644
index 2379dd40f8..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_MATRIX_H
-#define AT91_MATRIX_H
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x11C)
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x30)
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0	(ATMEL_BASE_MATRIX + 0x128)
-#else
-#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
-#endif
-
-#define AT91_ASM_MATRIX_MCFG	ATMEL_BASE_MATRIX
-
-#else
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_MATRIX_MASTERS	6
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9261)
-#define AT91_MATRIX_MASTERS	1
-#define AT91_MATRIX_SLAVES	5
-#elif defined(CONFIG_AT91SAM9263)
-#define AT91_MATRIX_MASTERS	9
-#define AT91_MATRIX_SLAVES	7
-#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MASTERS	11
-#define AT91_MATRIX_SLAVES	8
-#else
-#error CPU not supported. Please update at91_matrix.h
-#endif
-
-typedef struct at91_priority {
-	u32	a;
-	u32	b;
-} at91_priority_t;
-
-typedef struct at91_matrix {
-	u32		mcfg[AT91_MATRIX_MASTERS];
-#if defined(CONFIG_AT91SAM9261)
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		res61_1[3];
-	u32		tcr;
-	u32		res61_2[2];
-	u32		csa;
-	u32		pucr;
-	u32		res61_3[114];
-#else
-	u32		reserve1[16 - AT91_MATRIX_MASTERS];
-	u32		scfg[AT91_MATRIX_SLAVES];
-	u32		reserve2[16 - AT91_MATRIX_SLAVES];
-	at91_priority_t	pr[AT91_MATRIX_SLAVES];
-	u32		reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
-	u32		mrcr;		/* 0x100 Master Remap Control */
-	u32		reserve4[3];
-#if	defined(CONFIG_AT91SAM9G45)
-	u32		ccr[52];	/* 0x110 - 0x1E0 Chip Configuration */
-	u32		womr;		/* 0x1E4 Write Protect Mode  */
-	u32		wpsr;		/* 0x1E8 Write Protect Status */
-	u32		resg45_1[10];
-#elif defined(CONFIG_AT91SAM9260)  || defined(CONFIG_AT91SAM9G20)
-	u32		res60_1[3];
-	u32		csa;
-	u32		res60_2[56];
-#elif defined(CONFIG_AT91SAM9263)
-	u32		res63_1;
-	u32		tcmr;
-	u32		res63_2[2];
-	u32		csa[2];
-	u32		res63_3[54];
-#else
-	u32		reserve5[60];
-#endif
-#endif
-} at91_matrix_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_CSA_DBPUC		0x00000100
-#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V	0x00000000
-#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V	0x00010000
-
-#define AT91_MATRIX_CSA_EBI_CS1A	0x00000002
-#define AT91_MATRIX_CSA_EBI_CS3A	0x00000008
-#define AT91_MATRIX_CSA_EBI_CS4A	0x00000010
-#define AT91_MATRIX_CSA_EBI_CS5A	0x00000020
-
-#define AT91_MATRIX_CSA_EBI1_CS2A	0x00000008
-
-#if defined CONFIG_AT91SAM9261
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MCFG_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MCFG_RCB1	(1 << 1)
-#endif
-
-/* Undefined Length Burst Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_INFINITE	0x00000000
-#define AT91_MATRIX_MCFG_ULBT_SINGLE	0x00000001
-#define AT91_MATRIX_MCFG_ULBT_FOUR	0x00000002
-#define AT91_MATRIX_MCFG_ULBT_EIGHT	0x00000003
-#define AT91_MATRIX_MCFG_ULBT_SIXTEEN	0x00000004
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO	0x00000005
-#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR	0x00000006
-#define AT91_MATRIX_MCFG_ULBT_128	0x00000007
-#endif
-
-/* Default Master Type */
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE	0x00000000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST	0x00010000
-#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	0x00020000
-
-/* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 0xf) << 18)
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
-#define	AT91_MATRIX_SCFG_FIXED_DEFMSTR(x)	((x & 7) << 18)
-#endif
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0x1ff) << 0)
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_SLOT_CYCLE(x)	((x & 0xff) << 0)
-#endif
-
-/* Arbitration Type */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
-#define	AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN	0x00000000
-#define	AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	0x01000000
-#endif
-
-/* Master Remap Control Register */
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
-	defined(CONFIG_AT91SAM9G45)
-/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define	AT91_MATRIX_MRCR_RCB0	(1 << 0)
-/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define	AT91_MATRIX_MRCR_RCB1	(1 << 1)
-#endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB2	0x00000004
-#define	AT91_MATRIX_MRCR_RCB3	0x00000008
-#define	AT91_MATRIX_MRCR_RCB4	0x00000010
-#define	AT91_MATRIX_MRCR_RCB5	0x00000020
-#define	AT91_MATRIX_MRCR_RCB6	0x00000040
-#define	AT91_MATRIX_MRCR_RCB7	0x00000080
-#define	AT91_MATRIX_MRCR_RCB8	0x00000100
-#endif
-#if defined(CONFIG_AT91SAM9G45)
-#define	AT91_MATRIX_MRCR_RCB9	0x00000200
-#define	AT91_MATRIX_MRCR_RCB10	0x00000400
-#define	AT91_MATRIX_MRCR_RCB11	0x00000800
-#endif
-
-/* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000040
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-/* Wait state TCM register */
-#define	AT91_MATRIX_TCMR_TCM_NO_WS	0x00000000
-#define	AT91_MATRIX_TCMR_TCM_ONE_WS	0x00000800
-#endif
-#if defined(CONFIG_AT91SAM9263)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#endif
-#if defined(CONFIG_AT91SAM9261)
-/* Size of ITCM enabled memory block */
-#define	AT91_MATRIX_TCMR_ITCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_ITCM_16	0x00000005
-#define	AT91_MATRIX_TCMR_ITCM_32	0x00000006
-#define	AT91_MATRIX_TCMR_ITCM_64	0x00000007
-/* Size of DTCM enabled memory block */
-#define	AT91_MATRIX_TCMR_DTCM_0		0x00000000
-#define	AT91_MATRIX_TCMR_DTCM_16	0x00000050
-#define	AT91_MATRIX_TCMR_DTCM_32	0x00000060
-#define	AT91_MATRIX_TCMR_DTCM_64	0x00000070
-#endif
-
-#if defined(CONFIG_AT91SAM9G45)
-/* Video Mode Configuration Register */
-#define	AT91C_MATRIX_VDEC_SEL_OFF	0x00000000
-#define	AT91C_MATRIX_VDEC_SEL_ON	0x00000001
-/* Write Protect Mode Register */
-#define	AT91_MATRIX_WPMR_WP_WPDIS	0x00000000
-#define	AT91_MATRIX_WPMR_WP_WPEN	0x00000001
-#define	AT91_MATRIX_WPMR_WPKEY		0xFFFFFF00	/* Write Protect KEY */
-/* Write Protect Status Register */
-#define	AT91_MATRIX_WPSR_NO_WPV		0x00000000
-#define	AT91_MATRIX_WPSR_WPV		0x00000001
-#define	AT91_MATRIX_WPSR_WPVSRC		0x00FFFF00	/* Write Protect Violation Source */
-#endif
-
-/* USB Pad Pull-Up Control Register */
-#if defined(CONFIG_AT91SAM9261)
-#define	AT91_MATRIX_USBPUCR_PUON	0x40000000
-#endif
-
-#define AT91_MATRIX_PRA_M0(x)	((x & 3) << 0)	/* Master 0 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M1(x)	((x & 3) << 4)	/* Master 1 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M2(x)	((x & 3) << 8)	/* Master 2 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M3(x)	((x & 3) << 12)	/* Master 3 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M4(x)	((x & 3) << 16)	/* Master 4 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M5(x)	((x & 3) << 20)	/* Master 5 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M6(x)	((x & 3) << 24)	/* Master 6 Priority Reg. A*/
-#define AT91_MATRIX_PRA_M7(x)	((x & 3) << 28)	/* Master 7 Priority Reg. A*/
-#define AT91_MATRIX_PRB_M8(x)	((x & 3) << 0)	/* Master 8 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M9(x)	((x & 3) << 4)	/* Master 9 Priority Reg. B) */
-#define AT91_MATRIX_PRB_M10(x)	((x & 3) << 8)	/* Master 10 Priority Reg. B) */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h
deleted file mode 100644
index 2ace77931d..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_mc.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_MC_H
-#define AT91_MC_H
-
-#define AT91_ASM_MC_EBI_CSA	(ATMEL_BASE_MC + 0x60)
-#define AT91_ASM_MC_EBI_CFG	(ATMEL_BASE_MC + 0x64)
-#define AT91_ASM_MC_SMC_CSR0	(ATMEL_BASE_MC + 0x70)
-#define AT91_ASM_MC_SDRAMC_MR	(ATMEL_BASE_MC + 0x90)
-#define AT91_ASM_MC_SDRAMC_TR	(ATMEL_BASE_MC + 0x94)
-#define AT91_ASM_MC_SDRAMC_CR	(ATMEL_BASE_MC + 0x98)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_ebi {
-	u32 	csa;		/* 0x00 Chip Select Assignment Register */
-	u32	cfgr;		/* 0x04 Configuration Register */
-	u32	reserved[2];
-} at91_ebi_t;
-
-#define AT91_EBI_CSA_CS0A	0x0001
-#define AT91_EBI_CSA_CS1A	0x0002
-
-#define AT91_EBI_CSA_CS3A	0x0008
-#define AT91_EBI_CSA_CS4A	0x0010
-
-typedef struct at91_sdramc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
-	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
-	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
-	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
-	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
-	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
-	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
-	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
-	u32	reserved[3];
-} at91_sdramc_t;
-
-typedef struct at91_smc {
-	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
-} at91_smc_t;
-
-#define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
-#define AT91_SMC_CSR_RWSETUP(x)		((x & 0x7) << 24)
-#define AT91_SMC_CSR_ACSS_STANDARD	0x00000000
-#define AT91_SMC_CSR_ACSS_1CYCLE	0x00010000
-#define AT91_SMC_CSR_ACSS_2CYCLE	0x00020000
-#define AT91_SMC_CSR_ACSS_3CYCLE	0x00030000
-#define AT91_SMC_CSR_DRP		0x00008000
-#define AT91_SMC_CSR_DBW_8		0x00004000
-#define AT91_SMC_CSR_DBW_16		0x00002000
-#define AT91_SMC_CSR_BAT_8		0x00000000
-#define AT91_SMC_CSR_BAT_16		0x00001000
-#define AT91_SMC_CSR_TDF(x)		((x & 0xF) << 8)
-#define AT91_SMC_CSR_WSEN		0x00000080
-#define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
-
-typedef struct at91_bfc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-} at91_bfc_t;
-
-typedef struct at91_mc {
-	u32		rcr;		/* 0x00 MC Remap Control Register */
-	u32		asr;		/* 0x04 MC Abort Status Register */
-	u32		aasr;		/* 0x08 MC Abort Address Status Reg */
-	u32		mpr;		/* 0x0C MC Master Priority Register */
-	u32		reserved1[20];	/* 0x10-0x5C */
-	at91_ebi_t	ebi;		/* 0x60	- 0x6C EBI */
-	at91_smc_t	smc;		/* 0x70 - 0x8C SMC User Interface */
-	at91_sdramc_t	sdramc;		/* 0x90 - 0xBC SDRAMC User Interface */
-	at91_bfc_t	bfc;		/* 0xC0 BFC User Interface */
-	u32		reserved2[15];
-} at91_mc_t;
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pdc.h b/arch/arm/include/asm/arch-at91/at91_pdc.h
deleted file mode 100644
index 832ebb51c1..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_pdc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_PDC_H
-#define AT91_PDC_H
-
-typedef struct at91_pdc {
-	u32	rpr;		/* 0x100 Receive Pointer Register */
-	u32	rcr;		/* 0x104 Receive Counter Register */
-	u32	tpr;		/* 0x108 Transmit Pointer Register */
-	u32	tcr;		/* 0x10C Transmit Counter Register */
-	u32	pnpr;		/* 0x110 Receive Next Pointer Register */
-	u32	pncr;		/* 0x114 Receive Next Counter Register */
-	u32	tnpr;		/* 0x118 Transmit Next Pointer Register */
-	u32	tncr;		/* 0x11C Transmit Next Counter Register */
-	u32	ptcr;		/* 0x120 Transfer Control Register */
-	u32	ptsr;		/* 0x124 Transfer Status Register */
-} at91_pdc_t;
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
deleted file mode 100644
index 50464ffe8e..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Parallel I/O Controller (PIO) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_PIO_H
-#define AT91_PIO_H
-
-
-#define AT91_ASM_PIO_RANGE	0x200
-#define AT91_ASM_PIOC_ASR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)
-#define AT91_ASM_PIOC_BSR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74)
-#define AT91_ASM_PIOC_PDR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOC_PUDR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60)
-
-#define AT91_ASM_PIOD_PDR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04)
-#define AT91_ASM_PIOD_PUDR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60)
-#define AT91_ASM_PIOD_ASR	\
-	(ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_port {
-	u32	per;		/* 0x00 PIO Enable Register */
-	u32	pdr;		/* 0x04 PIO Disable Register */
-	u32	psr;		/* 0x08 PIO Status Register */
-	u32	reserved0;
-	u32	oer;		/* 0x10 Output Enable Register */
-	u32	odr;		/* 0x14 Output Disable Registerr */
-	u32	osr;		/* 0x18 Output Status Register */
-	u32	reserved1;
-	u32	ifer;		/* 0x20 Input Filter Enable Register */
-	u32	ifdr;		/* 0x24 Input Filter Disable Register */
-	u32	ifsr;		/* 0x28 Input Filter Status Register */
-	u32	reserved2;
-	u32	sodr;		/* 0x30 Set Output Data Register */
-	u32	codr;		/* 0x34 Clear Output Data Register */
-	u32	odsr;		/* 0x38 Output Data Status Register */
-	u32	pdsr;		/* 0x3C Pin Data Status Register */
-	u32	ier;		/* 0x40 Interrupt Enable Register */
-	u32	idr;		/* 0x44 Interrupt Disable Register */
-	u32	imr;		/* 0x48 Interrupt Mask Register */
-	u32	isr;		/* 0x4C Interrupt Status Register */
-	u32	mder;		/* 0x50 Multi-driver Enable Register */
-	u32	mddr;		/* 0x54 Multi-driver Disable Register */
-	u32	mdsr;		/* 0x58 Multi-driver Status Register */
-	u32	reserved3;
-	u32	pudr;		/* 0x60 Pull-up Disable Register */
-	u32	puer;		/* 0x64 Pull-up Enable Register */
-	u32	pusr;		/* 0x68 Pad Pull-up Status Register */
-	u32	reserved4;
-#if defined(CPU_HAS_PIO3)
-	u32	abcdsr1;	/* 0x70 Peripheral ABCD Select Register 1 */
-	u32	abcdsr2;	/* 0x74 Peripheral ABCD Select Register 2 */
-	u32	reserved5[2];
-	u32	ifscdr;		/* 0x80 Input Filter SCLK Disable Register */
-	u32	ifscer;		/* 0x84 Input Filter SCLK Enable Register */
-	u32	ifscsr;		/* 0x88 Input Filter SCLK Status Register */
-	u32	scdr;		/* 0x8C SCLK Divider Debouncing Register */
-	u32	ppddr;		/* 0x90 Pad Pull-down Disable Register */
-	u32	ppder;		/* 0x94 Pad Pull-down Enable Register */
-	u32	ppdsr;		/* 0x98 Pad Pull-down Status Register */
-	u32	reserved6;	/*  */
-#else
-	u32	asr;		/* 0x70 Select A Register */
-	u32	bsr;		/* 0x74 Select B Register */
-	u32	absr;		/* 0x78 AB Select Status Register */
-	u32	reserved5[9];	/*  */
-#endif
-	u32	ower;		/* 0xA0 Output Write Enable Register */
-	u32	owdr;		/* 0xA4 Output Write Disable Register */
-	u32	owsr;		/* OxA8 Output Write Status Register */
-#if defined(CPU_HAS_PIO3)
-	u32	reserved7;	/*  */
-	u32	aimer;		/* 0xB0 Additional INT Modes Enable Register */
-	u32	aimdr;		/* 0xB4 Additional INT Modes Disable Register */
-	u32	aimmr;		/* 0xB8 Additional INT Modes Mask Register */
-	u32	reserved8;	/* */
-	u32	esr;		/* 0xC0 Edge Select Register */
-	u32	lsr;		/* 0xC4 Level Select Register */
-	u32	elsr;		/* 0xC8 Edge/Level Status Register */
-	u32	reserved9;	/* 0xCC */
-	u32	fellsr;		/* 0xD0 Falling /Low Level Select Register */
-	u32	rehlsr;		/* 0xD4 Rising /High Level Select Register */
-	u32	frlhsr;		/* 0xD8 Fall/Rise - Low/High Status Register */
-	u32	reserved10;	/* */
-	u32	locksr;		/* 0xE0 Lock Status */
-	u32	wpmr;		/* 0xE4 Write Protect Mode Register */
-	u32	wpsr;		/* 0xE8 Write Protect Status Register */
-	u32	reserved11[5];	/* */
-	u32	schmitt;	/* 0x100 Schmitt Trigger Register */
-	u32	reserved12[63];
-#else
-	u32	reserved6[85];
-#endif
-} at91_port_t;
-
-typedef union at91_pio {
-	struct {
-		at91_port_t	pioa;
-		at91_port_t	piob;
-		at91_port_t	pioc;
-	#if (ATMEL_PIO_PORTS > 3)
-		at91_port_t	piod;
-	#endif
-	#if (ATMEL_PIO_PORTS > 4)
-		at91_port_t	pioe;
-	#endif
-	} ;
-	at91_port_t port[ATMEL_PIO_PORTS];
-} at91_pio_t;
-
-#ifdef CONFIG_AT91_GPIO
-int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
-#if defined(CPU_HAS_PIO3)
-int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
-int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
-#endif
-int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_output(unsigned port, unsigned pin, int value);
-int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup);
-int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on);
-int at91_set_pio_value(unsigned port, unsigned pin, int value);
-int at91_get_pio_value(unsigned port, unsigned pin);
-#endif
-#endif
-
-#define	AT91_PIO_PORTA		0x0
-#define	AT91_PIO_PORTB		0x1
-#define	AT91_PIO_PORTC		0x2
-#define	AT91_PIO_PORTD		0x3
-#define	AT91_PIO_PORTE		0x4
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h
deleted file mode 100644
index 56724f15e7..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Periodic Interval Timer (PIT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_PIT_H
-#define AT91_PIT_H
-
-typedef struct at91_pit {
-	u32	mr;	/* 0x00 Mode Register */
-	u32	sr;	/* 0x04 Status Register */
-	u32	pivr;	/* 0x08 Periodic Interval Value Register */
-	u32	piir;	/* 0x0C Periodic Interval Image Register */
-} at91_pit_t;
-
-#define		AT91_PIT_MR_IEN		0x02000000
-#define		AT91_PIT_MR_EN		0x01000000
-#define		AT91_PIT_MR_PIV_MASK(x)	(x & 0x000fffff)
-#define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
deleted file mode 100644
index 65691aba01..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * Power Management Controller (PMC) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_PMC_H
-#define AT91_PMC_H
-
-#ifdef __ASSEMBLY__
-
-#define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
-#define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
-#define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
-#define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
-#define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
-
-#else
-
-#include <asm/types.h>
-
-typedef struct at91_pmc {
-	u32	scer;		/* 0x00 System Clock Enable Register */
-	u32	scdr;		/* 0x04 System Clock Disable Register */
-	u32	scsr;		/* 0x08 System Clock Status Register */
-	u32	reserved0;
-	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
-	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
-	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
-	u32	uckr;		/* 0x1C UTMI Clock Register */
-	u32	mor;		/* 0x20 Main Oscilator Register */
-	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
-	u32	pllar;		/* 0x28 PLL A Register */
-	u32	pllbr;		/* 0x2C PLL B Register */
-	u32	mckr;		/* 0x30 Master Clock Register */
-	u32	reserved1;
-	u32	usb;		/* 0x38 USB Clock Register */
-	u32	reserved2;
-	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
-	u32	reserved3[4];
-	u32	ier;		/* 0x60 Interrupt Enable Register */
-	u32	idr;		/* 0x64 Interrupt Disable Register */
-	u32	sr;		/* 0x68 Status Register */
-	u32	imr;		/* 0x6C Interrupt Mask Register */
-	u32	reserved4[4];
-	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
-	u32	reserved5[21];
-	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
-	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CPU_HAS_PCR
-	u32	reserved6[8];
-	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
-	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
-	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
-	u32	pcr;		/* 0x10c Periperial Control Register */
-	u32	ocr;		/* 0x110 Oscillator Calibration Register */
-#else
-	u32	reserved8[5];
-#endif
-} at91_pmc_t;
-
-#endif	/* end not assembly */
-
-#define AT91_PMC_MOR_MOSCEN		0x01
-#define AT91_PMC_MOR_OSCBYPASS		0x02
-#define AT91_PMC_MOR_MOSCRCEN		0x08
-#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
-#define AT91_PMC_MOR_KEY(x)		((x & 0xff) << 16)
-#define AT91_PMC_MOR_MOSCSEL		(1 << 24)
-
-#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
-#else
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
-#endif
-#define AT91_PMC_PLLAR_29		0x20000000
-#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
-#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
-#define AT91_PMC_PLLBR_USBDIV_4		0x20000000
-
-#define AT91_PMC_MCFR_MAINRDY		0x00010000
-#define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF
-
-#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
-#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
-#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
-#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
-#define AT91_PMC_MCKR_CSS_MASK		0x00000003
-
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_MCKR_PRES_1		0x00000000
-#define AT91_PMC_MCKR_PRES_2		0x00000010
-#define AT91_PMC_MCKR_PRES_4		0x00000020
-#define AT91_PMC_MCKR_PRES_8		0x00000030
-#define AT91_PMC_MCKR_PRES_16		0x00000040
-#define AT91_PMC_MCKR_PRES_32		0x00000050
-#define AT91_PMC_MCKR_PRES_64		0x00000060
-#define AT91_PMC_MCKR_PRES_MASK		0x00000070
-#else
-#define AT91_PMC_MCKR_PRES_1		0x00000000
-#define AT91_PMC_MCKR_PRES_2		0x00000004
-#define AT91_PMC_MCKR_PRES_4		0x00000008
-#define AT91_PMC_MCKR_PRES_8		0x0000000C
-#define AT91_PMC_MCKR_PRES_16		0x00000010
-#define AT91_PMC_MCKR_PRES_32		0x00000014
-#define AT91_PMC_MCKR_PRES_64		0x00000018
-#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
-#endif
-
-#ifdef CONFIG_AT91RM9200
-#define AT91_PMC_MCKR_MDIV_1		0x00000000
-#define AT91_PMC_MCKR_MDIV_2		0x00000100
-#define AT91_PMC_MCKR_MDIV_3		0x00000200
-#define AT91_PMC_MCKR_MDIV_4		0x00000300
-#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
-#else
-#define AT91_PMC_MCKR_MDIV_1		0x00000000
-#define AT91_PMC_MCKR_MDIV_2		0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_MCKR_MDIV_3		0x00000300
-#endif
-#define AT91_PMC_MCKR_MDIV_4		0x00000200
-#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
-#endif
-
-#define AT91_PMC_MCKR_PLLADIV_MASK	0x00003000
-#define AT91_PMC_MCKR_PLLADIV_1		0x00000000
-#define AT91_PMC_MCKR_PLLADIV_2		0x00001000
-
-#define AT91_PMC_MCKR_H32MXDIV		0x01000000
-
-#define AT91_PMC_IXR_MOSCS		0x00000001
-#define AT91_PMC_IXR_LOCKA		0x00000002
-#define AT91_PMC_IXR_LOCKB		0x00000004
-#define AT91_PMC_IXR_MCKRDY		0x00000008
-#define AT91_PMC_IXR_LOCKU		0x00000040
-#define AT91_PMC_IXR_PCKRDY0		0x00000100
-#define AT91_PMC_IXR_PCKRDY1		0x00000200
-#define AT91_PMC_IXR_PCKRDY2		0x00000400
-#define AT91_PMC_IXR_PCKRDY3		0x00000800
-#define AT91_PMC_IXR_MOSCSELS		0x00010000
-
-#define AT91_PMC_PCR_PID_MASK		(0x3f)
-#define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
-#define AT91_PMC_PCR_EN			(0x1 << 28)
-
-#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
-#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
-#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
-#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
-#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
-#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
-#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
-#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
-#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
-#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
-
-#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x] */
-#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-
-#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-
-#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
-#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
-#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
-#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
-#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
-#define			AT91_PMC_USBDIV_1		(0 << 28)
-#define			AT91_PMC_USBDIV_2		(1 << 28)
-#define			AT91_PMC_USBDIV_4		(2 << 28)
-#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
-#define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
-
-#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
-#define			AT91_PMC_CSS_SLOW		(0 << 0)
-#define			AT91_PMC_CSS_MAIN		(1 << 0)
-#define			AT91_PMC_CSS_PLLA		(2 << 0)
-#define			AT91_PMC_CSS_PLLB		(3 << 0)
-#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
-#define			AT91_PMC_PRES_1			(0 << 2)
-#define			AT91_PMC_PRES_2			(1 << 2)
-#define			AT91_PMC_PRES_4			(2 << 2)
-#define			AT91_PMC_PRES_8			(3 << 2)
-#define			AT91_PMC_PRES_16		(4 << 2)
-#define			AT91_PMC_PRES_32		(5 << 2)
-#define			AT91_PMC_PRES_64		(6 << 2)
-#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
-#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
-#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
-#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
-#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
-#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
-#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_6		(3 << 8)
-#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
-#define			AT91_PMC_PDIV_1			(0 << 12)
-#define			AT91_PMC_PDIV_2			(1 << 12)
-
-#define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
-#define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
-#define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
-#define		AT91_PMC_USB_DIV_2		(0x1 <<  8)	/* USB Clock divided by 2 */
-#define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
-#define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
-
-#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
-#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
-#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
-#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
-#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock */
-#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-
-#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h
deleted file mode 100644
index e4eb3da03f..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Reset Controller (RSTC) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_RSTC_H
-#define AT91_RSTC_H
-
-/* Reset Controller Status Register */
-#define AT91_ASM_RSTC_SR	(ATMEL_BASE_RSTC + 0x04)
-#define AT91_ASM_RSTC_MR	(ATMEL_BASE_RSTC + 0x08)
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rstc {
-	u32	cr;	/* Reset Controller Control Register */
-	u32	sr;	/* Reset Controller Status Register */
-	u32	mr;	/* Reset Controller Mode Register */
-} at91_rstc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RSTC_KEY		0xA5000000
-
-#define AT91_RSTC_CR_PROCRST	0x00000001
-#define AT91_RSTC_CR_PERRST	0x00000004
-#define AT91_RSTC_CR_EXTRST	0x00000008
-
-#define AT91_RSTC_MR_URSTEN	0x00000001
-#define AT91_RSTC_MR_URSTIEN	0x00000010
-#define AT91_RSTC_MR_ERSTL(x)	((x & 0xf) << 8)
-#define AT91_RSTC_MR_ERSTL_MASK	0x0000FF00
-
-#define AT91_RSTC_SR_NRSTL	0x00010000
-
-#define AT91_RSTC_RSTTYP		(7 << 8)	/* Reset Type */
-#define AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
-#define AT91_RSTC_RSTTYP_WAKEUP	(1 << 8)
-#define AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
-#define AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
-#define AT91_RSTC_RSTTYP_USER		(4 << 8)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/include/asm/arch-at91/at91_rtt.h
deleted file mode 100644
index fe7619a932..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_rtt.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Real-time Timer
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_RTT_H
-#define AT91_RTT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_rtt {
-	u32	mr;	/* Mode Register   RW 0x00008000 */
-	u32	ar;	/* Alarm Register  RW 0xFFFFFFFF */
-	u32	vr;	/* Value Register  RO 0x00000000 */
-	u32	sr;	/* Status Register RO 0x00000000 */
-} at91_rtt_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_RTT_MR_RTPRES	0x0000ffff
-#define AT91_RTT_MR_ALMIEN	0x00010000
-#define AT91_RTT_RTTINCIEN	0x00020000
-#define AT91_RTT_RTTRST	0x00040000
-
-#define AT91_RTT_SR_ALMS	0x00000001
-#define AT91_RTT_SR_RTTINC	0x00000002
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
deleted file mode 100644
index b18665b62c..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#include <asm/arch/at91_pdc.h>
-
-typedef struct at91_spi {
-	u32		cr;		/* 0x00 Control Register */
-	u32		mr;		/* 0x04 Mode Register */
-	u32		rdr;		/* 0x08 Receive Data Register */
-	u32		tdr;		/* 0x0C Transmit Data Register */
-	u32		sr;		/* 0x10 Status Register */
-	u32		ier;		/* 0x14 Interrupt Enable Register */
-	u32		idr;		/* 0x18 Interrupt Disable Register */
-	u32		imr;		/* 0x1C Interrupt Mask Register */
-	u32		reserve1[4];
-	u32		csr[4];		/* 0x30 Chip Select Register 0-3 */
-	u32		reserve2[48];
-	at91_pdc_t	pdc;
-} at91_spi_t;
-
-#ifdef CONFIG_ATMEL_LEGACY
-
-#define AT91_SPI_CR			0x00		/* Control Register */
-#define		AT91_SPI_SPIEN		(1 <<  0)		/* SPI Enable */
-#define		AT91_SPI_SPIDIS		(1 <<  1)		/* SPI Disable */
-#define		AT91_SPI_SWRST		(1 <<  7)		/* SPI Software Reset */
-#define		AT91_SPI_LASTXFER	(1 << 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR			0x04		/* Mode Register */
-#define		AT91_SPI_MSTR		(1    <<  0)		/* Master/Slave Mode */
-#define		AT91_SPI_PS		(1    <<  1)		/* Peripheral Select */
-#define			AT91_SPI_PS_FIXED	(0 << 1)
-#define			AT91_SPI_PS_VARIABLE	(1 << 1)
-#define		AT91_SPI_PCSDEC		(1    <<  2)		/* Chip Select Decode */
-#define		AT91_SPI_DIV32		(1    <<  3)		/* Clock Selection [AT91RM9200 only] */
-#define		AT91_SPI_MODFDIS	(1    <<  4)		/* Mode Fault Detection */
-#define		AT91_SPI_LLB		(1    <<  7)		/* Local Loopback Enable */
-#define		AT91_SPI_PCS		(0xf  << 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_DLYBCS		(0xff << 24)		/* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR		0x08			/* Receive Data Register */
-#define		AT91_SPI_RD		(0xffff <<  0)		/* Receive Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-
-#define AT91_SPI_TDR		0x0c			/* Transmit Data Register */
-#define		AT91_SPI_TD		(0xffff <<  0)		/* Transmit Data */
-#define		AT91_SPI_PCS		(0xf	<< 16)		/* Peripheral Chip Select */
-#define		AT91_SPI_LASTXFER	(1	<< 24)		/* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR		0x10			/* Status Register */
-#define		AT91_SPI_RDRF		(1 <<  0)		/* Receive Data Register Full */
-#define		AT91_SPI_TDRE		(1 <<  1)		/* Transmit Data Register Full */
-#define		AT91_SPI_MODF		(1 <<  2)		/* Mode Fault Error */
-#define		AT91_SPI_OVRES		(1 <<  3)		/* Overrun Error Status */
-#define		AT91_SPI_ENDRX		(1 <<  4)		/* End of RX buffer */
-#define		AT91_SPI_ENDTX		(1 <<  5)		/* End of TX buffer */
-#define		AT91_SPI_RXBUFF		(1 <<  6)		/* RX Buffer Full */
-#define		AT91_SPI_TXBUFE		(1 <<  7)		/* TX Buffer Empty */
-#define		AT91_SPI_NSSR		(1 <<  8)		/* NSS Rising [SAM9261 only] */
-#define		AT91_SPI_TXEMPTY	(1 <<  9)		/* Transmission Register Empty [SAM9261 only] */
-#define		AT91_SPI_SPIENS		(1 << 16)		/* SPI Enable Status */
-
-#define AT91_SPI_IER		0x14			/* Interrupt Enable Register */
-#define AT91_SPI_IDR		0x18			/* Interrupt Disable Register */
-#define AT91_SPI_IMR		0x1c			/* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)		(0x30 + ((n) * 4))	/* Chip Select Registers 0-3 */
-#define		AT91_SPI_CPOL		(1    <<  0)		/* Clock Polarity */
-#define		AT91_SPI_NCPHA		(1    <<  1)		/* Clock Phase */
-#define		AT91_SPI_CSAAT		(1    <<  3)		/* Chip Select Active After Transfer [SAM9261 only] */
-#define		AT91_SPI_BITS		(0xf  <<  4)		/* Bits Per Transfer */
-#define			AT91_SPI_BITS_8		(0 << 4)
-#define			AT91_SPI_BITS_9		(1 << 4)
-#define			AT91_SPI_BITS_10	(2 << 4)
-#define			AT91_SPI_BITS_11	(3 << 4)
-#define			AT91_SPI_BITS_12	(4 << 4)
-#define			AT91_SPI_BITS_13	(5 << 4)
-#define			AT91_SPI_BITS_14	(6 << 4)
-#define			AT91_SPI_BITS_15	(7 << 4)
-#define			AT91_SPI_BITS_16	(8 << 4)
-#define		AT91_SPI_SCBR		(0xff <<  8)		/* Serial Clock Baud Rate */
-#define		AT91_SPI_DLYBS		(0xff << 16)		/* Delay before SPCK */
-#define		AT91_SPI_DLYBCT		(0xff << 24)		/* Delay between Consecutive Transfers */
-
-#define AT91_SPI_RPR		0x0100			/* Receive Pointer Register */
-
-#define AT91_SPI_RCR		0x0104			/* Receive Counter Register */
-
-#define AT91_SPI_TPR		0x0108			/* Transmit Pointer Register */
-
-#define AT91_SPI_TCR		0x010c			/* Transmit Counter Register */
-
-#define AT91_SPI_RNPR		0x0110			/* Receive Next Pointer Register */
-
-#define AT91_SPI_RNCR		0x0114			/* Receive Next Counter Register */
-
-#define AT91_SPI_TNPR		0x0118			/* Transmit Next Pointer Register */
-
-#define AT91_SPI_TNCR		0x011c			/* Transmit Next Counter Register */
-
-#define AT91_SPI_PTCR		0x0120			/* PDC Transfer Control Register */
-#define		AT91_SPI_RXTEN		(0x1 << 0)		/* Receiver Transfer Enable */
-#define		AT91_SPI_RXTDIS		(0x1 << 1)		/* Receiver Transfer Disable */
-#define		AT91_SPI_TXTEN		(0x1 << 8)		/* Transmitter Transfer Enable */
-#define		AT91_SPI_TXTDIS		(0x1 << 9)		/* Transmitter Transfer Disable */
-
-#define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
-
-#endif /* CONFIG_ATMEL_LEGACY */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/include/asm/arch-at91/at91_st.h
deleted file mode 100644
index b1ee1472e5..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_st.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-typedef struct at91_st {
-
-	u32	cr;
-	u32	pimr;
-	u32	wdmr;
-	u32	rtmr;
-	u32	sr;
-	u32	ier;
-	u32	idr;
-	u32	imr;
-	u32	rtar;
-	u32	crtr;
-} at91_st_t ;
-
-#define AT91_ST_CR_WDRST	1
-
-#define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
-#define AT91_ST_WDMR_RSTEN	0x00010000
-#define AT91_ST_WDMR_EXTEN 	0x00020000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/include/asm/arch-at91/at91_tc.h
deleted file mode 100644
index de0e266565..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_tc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-typedef struct at91_tcc {
-	u32		ccr;	/* 0x00 Channel Control Register */
-	u32		cmr;	/* 0x04 Channel Mode Register */
-	u32		reserved1[2];
-	u32		cv;	/* 0x10 Counter Value */
-	u32		ra;	/* 0x14 Register A */
-	u32		rb;	/* 0x18 Register B */
-	u32		rc;	/* 0x1C Register C */
-	u32		sr;	/* 0x20 Status Register */
-	u32		ier;	/* 0x24 Interrupt Enable Register */
-	u32		idr;	/* 0x28 Interrupt Disable Register */
-	u32		imr;	/* 0x2C Interrupt Mask Register */
-	u32		reserved3[4];
-} at91_tcc_t;
-
-#define AT91_TC_CCR_CLKEN		0x00000001
-#define AT91_TC_CCR_CLKDIS		0x00000002
-#define AT91_TC_CCR_SWTRG		0x00000004
-
-#define AT91_TC_CMR_CPCTRG		0x00004000
-
-#define AT91_TC_CMR_TCCLKS_CLOCK1	0x00000000
-#define AT91_TC_CMR_TCCLKS_CLOCK2	0x00000001
-#define AT91_TC_CMR_TCCLKS_CLOCK3	0x00000002
-#define AT91_TC_CMR_TCCLKS_CLOCK4	0x00000003
-#define AT91_TC_CMR_TCCLKS_CLOCK5	0x00000004
-#define AT91_TC_CMR_TCCLKS_XC0		0x00000005
-#define AT91_TC_CMR_TCCLKS_XC1		0x00000006
-#define AT91_TC_CMR_TCCLKS_XC2		0x00000007
-
-typedef struct at91_tc {
-	at91_tcc_t	tc[3];	/* 0x00 TC Channel 0-2 */
-	u32		bcr;	/* 0xC0 TC Block Control Register */
-	u32		bmr;	/* 0xC4 TC Block Mode Register */
-} at91_tc_t;
-
-#define AT91_TC_BMR_TC0XC0S_TCLK0	0x00000000
-#define AT91_TC_BMR_TC0XC0S_NONE	0x00000001
-#define AT91_TC_BMR_TC0XC0S_TIOA1	0x00000002
-#define AT91_TC_BMR_TC0XC0S_TIOA2	0x00000003
-
-#define AT91_TC_BMR_TC1XC1S_TCLK1	0x00000000
-#define AT91_TC_BMR_TC1XC1S_NONE	0x00000004
-#define AT91_TC_BMR_TC1XC1S_TIOA0	0x00000008
-#define AT91_TC_BMR_TC1XC1S_TIOA2	0x0000000C
-
-#define AT91_TC_BMR_TC2XC2S_TCLK2	0x00000000
-#define AT91_TC_BMR_TC2XC2S_NONE	0x00000010
-#define AT91_TC_BMR_TC2XC2S_TIOA0	0x00000020
-#define AT91_TC_BMR_TC2XC2S_TIOA1	0x00000030
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h
deleted file mode 100644
index 0644bbf3c6..0000000000
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Watchdog Timer (WDT) - System peripherals regsters.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91_WDT_H
-#define AT91_WDT_H
-
-#ifdef __ASSEMBLY__
-
-#define AT91_ASM_WDT_MR	(ATMEL_BASE_WDT +  0x04)
-
-#else
-
-typedef struct at91_wdt {
-	u32	cr;
-	u32	mr;
-	u32	sr;
-} at91_wdt_t;
-
-#endif
-
-#define AT91_WDT_CR_WDRSTT		1
-#define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
-
-#define AT91_WDT_MR_WDV(x)		(x & 0xfff)
-#define AT91_WDT_MR_WDFIEN		0x00001000
-#define AT91_WDT_MR_WDRSTEN		0x00002000
-#define AT91_WDT_MR_WDRPROC		0x00004000
-#define AT91_WDT_MR_WDDIS		0x00008000
-#define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
-#define AT91_WDT_MR_WDDBGHLT		0x10000000
-#define AT91_WDT_MR_WDIDLEHLT		0x20000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h
deleted file mode 100644
index d177bdcae5..0000000000
--- a/arch/arm/include/asm/arch-at91/at91rm9200.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AT91RM9200_H__
-#define __AT91RM9200_H__
-
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 family */
-#define CONFIG_ARCH_CPU_INIT	/* we need arch_cpu_init() for hw timers */
-#define CONFIG_AT91_GPIO	/* and require always gpio features */
-
-/* Periperial Identifiers */
-
-#define ATMEL_ID_SYS	1	/* System Peripheral */
-#define ATMEL_ID_PIOA	2	/* PIO port A */
-#define ATMEL_ID_PIOB	3	/* PIO port B */
-#define ATMEL_ID_PIOC	4	/* PIO port C */
-#define ATMEL_ID_PIOD	5	/* PIO port D BGA only */
-#define ATMEL_ID_USART0	6	/* USART 0 */
-#define ATMEL_ID_USART1	7	/* USART 1 */
-#define ATMEL_ID_USART2	8	/* USART 2 */
-#define ATMEL_ID_USART3	9	/* USART 3 */
-#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
-#define ATMEL_ID_UDP	11	/* USB Device Port */
-#define ATMEL_ID_TWI	12	/* Two Wire Interface */
-#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
-#define ATMEL_ID_SSC0	14	/* Synch. Serial Controller 0 */
-#define ATMEL_ID_SSC1	15	/* Synch. Serial Controller 1 */
-#define ATMEL_ID_SSC2	16	/* Synch. Serial Controller 2 */
-#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
-#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
-#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
-#define ATMEL_ID_TC3	20	/* Timer Counter 3 */
-#define ATMEL_ID_TC4	21	/* Timer Counter 4 */
-#define ATMEL_ID_TC5	22	/* Timer Counter 5 */
-#define ATMEL_ID_UHP	23	/* OHCI USB Host Port */
-#define ATMEL_ID_EMAC	24	/* Ethernet MAC */
-#define ATMEL_ID_IRQ0	25	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ1	26	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ2	27	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ3	28	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ4	29	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ5	30	/* Advanced Interrupt Controller */
-#define ATMEL_ID_IRQ6	31	/* Advanced Interrupt Controller */
-
-#define ATMEL_USB_HOST_BASE	0x00300000
-
-#define ATMEL_BASE_TC		0xFFFA0000
-#define ATMEL_BASE_UDP		0xFFFB0000
-#define ATMEL_BASE_MCI		0xFFFB4000
-#define ATMEL_BASE_TWI		0xFFFB8000
-#define ATMEL_BASE_EMAC		0xFFFBC000
-#define ATMEL_BASE_USART	0xFFFC0000	/* 4x 0x4000 Offset */
-#define ATMEL_BASE_USART0	ATMEL_BASE_USART
-#define ATMEL_BASE_USART1	(ATMEL_BASE_USART + 0x4000)
-#define ATMEL_BASE_USART2	(ATMEL_BASE_USART + 0x8000)
-#define ATMEL_BASE_USART3	(ATMEL_BASE_USART + 0xC000)
-
-#define ATMEL_BASE_SCC		0xFFFD0000	/* 4x 0x4000 Offset */
-#define ATMEL_BASE_SPI		0xFFFE0000
-
-#define ATMEL_BASE_AIC		0xFFFFF000
-#define ATMEL_BASE_DBGU		0xFFFFF200
-#define ATMEL_BASE_PIO		0xFFFFF400	/* 4x 0x200 Offset */
-#define ATMEL_BASE_PIOA		0xFFFFF400
-#define ATMEL_BASE_PIOB		0xFFFFF600
-#define ATMEL_BASE_PIOC		0xFFFFF800
-#define ATMEL_BASE_PIOD		0xFFFFFA00
-#define ATMEL_BASE_PMC		0xFFFFFC00
-#define ATMEL_BASE_ST		0xFFFFFD00
-#define ATMEL_BASE_RTC		0xFFFFFE00
-#define ATMEL_BASE_MC		0xFFFFFF00
-
-#define AT91_PIO_BASE	ATMEL_BASE_PIO
-
-/* AT91RM9200 Periperial Multiplexing A */
-/* Port A */
-#define ATMEL_PMX_AA_EREFCK	0x00000080
-#define ATMEL_PMX_AA_ETXCK	0x00000080
-#define ATMEL_PMX_AA_ETXEN	0x00000100
-#define ATMEL_PMX_AA_ETX0	0x00000200
-#define ATMEL_PMX_AA_ETX1	0x00000400
-#define ATMEL_PMX_AA_ECRS	0x00000800
-#define ATMEL_PMX_AA_ECRSDV	0x00000800
-#define ATMEL_PMX_AA_ERX0	0x00001000
-#define ATMEL_PMX_AA_ERX1	0x00002000
-#define ATMEL_PMX_AA_ERXER	0x00004000
-#define ATMEL_PMX_AA_EMDC	0x00008000
-#define ATMEL_PMX_AA_EMDIO	0x00010000
-
-#define ATMEL_PMX_AA_TXD2	0x00800000
-
-#define ATMEL_PMX_AA_TWD	0x02000000
-#define ATMEL_PMX_AA_TWCK	0x04000000
-
-/* Port B */
-#define ATMEL_PMX_BA_ERXCK	0x00080000
-#define ATMEL_PMX_BA_ECOL	0x00040000
-#define ATMEL_PMX_BA_ERXDV	0x00020000
-#define ATMEL_PMX_BA_ERX3	0x00010000
-#define ATMEL_PMX_BA_ERX2	0x00008000
-#define ATMEL_PMX_BA_ETXER	0x00004000
-#define ATMEL_PMX_BA_ETX3	0x00002000
-#define ATMEL_PMX_BA_ETX2	0x00001000
-
-/* Port B */
-
-#define ATMEL_PMX_CA_BFCK	0x00000001
-#define ATMEL_PMX_CA_BFRDY	0x00000002
-#define ATMEL_PMX_CA_SMOE	0x00000002
-#define ATMEL_PMX_CA_BFAVD	0x00000004
-#define ATMEL_PMX_CA_BFBAA	0x00000008
-#define ATMEL_PMX_CA_SMWE	0x00000008
-#define ATMEL_PMX_CA_BFOE	0x00000010
-#define ATMEL_PMX_CA_BFWE	0x00000020
-#define ATMEL_PMX_CA_NWAIT	0x00000040
-#define ATMEL_PMX_CA_A23	0x00000080
-#define ATMEL_PMX_CA_A24	0x00000100
-#define ATMEL_PMX_CA_A25	0x00000200
-#define ATMEL_PMX_CA_CFRNW	0x00000200
-#define ATMEL_PMX_CA_NCS4	0x00000400
-#define ATMEL_PMX_CA_CFCS	0x00000400
-#define ATMEL_PMX_CA_NCS5	0x00000800
-#define ATMEL_PMX_CA_CFCE1	0x00001000
-#define ATMEL_PMX_CA_NCS6	0x00001000
-#define ATMEL_PMX_CA_CFCE2	0x00002000
-#define ATMEL_PMX_CA_NCS7	0x00002000
-#define ATMEL_PMX_CA_D16_31	0xFFFF0000
-
-#define ATMEL_PIO_PORTS		4	/* theese SoCs have 4 PIO */
-#define ATMEL_PMC_UHP		AT91RM9200_PMC_UHP
-
-#define CONFIG_SYS_ATMEL_CPU_NAME	"AT91RM9200"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h
deleted file mode 100644
index 8950d67409..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9260.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
- *
- * (C) 2006 Andrew Victor
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoCs:
- * AT91SAM9260, AT91SAM9G20, AT91SAM9XE
- *
- * Note that those SoCs are mostly software and pin compatible,
- * therefore this file applies to all of them. Differences between
- * those SoCs are concentrated at the end of this file.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Peripherals */
-#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
-#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
-#define ATMEL_ID_ADC	5	/* Analog-to-Digital Converter */
-#define ATMEL_ID_USART0	6	/* USART 0 */
-#define ATMEL_ID_USART1	7	/* USART 1 */
-#define ATMEL_ID_USART2	8	/* USART 2 */
-#define ATMEL_ID_MCI	9	/* Multimedia Card Interface */
-#define ATMEL_ID_UDP	10	/* USB Device Port */
-#define ATMEL_ID_TWI0	11	/* Two-Wire Interface 0 */
-#define ATMEL_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-/* Reserved:		15 */
-/* Reserved:		16 */
-#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
-#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
-#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
-#define ATMEL_ID_UHP	20	/* USB Host port */
-#define ATMEL_ID_EMAC0	21	/* Ethernet 0 */
-#define ATMEL_ID_ISI	22	/* Image Sensor Interface */
-#define ATMEL_ID_USART3	23	/* USART 3 */
-#define ATMEL_ID_USART4	24	/* USART 4 */
-/* USART5 or TWI1:	25 */
-#define ATMEL_ID_TC3	26	/* Timer Counter 3 */
-#define ATMEL_ID_TC4	27	/* Timer Counter 4 */
-#define ATMEL_ID_TC5	28	/* Timer Counter 5 */
-#define ATMEL_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define ATMEL_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_TCB0		0xfffa0000
-#define ATMEL_BASE_TC0		0xfffa0000
-#define ATMEL_BASE_TC1		0xfffa0040
-#define ATMEL_BASE_TC2		0xfffa0080
-#define ATMEL_BASE_UDP0		0xfffa4000
-#define ATMEL_BASE_MCI		0xfffa8000
-#define ATMEL_BASE_TWI0		0xfffac000
-#define ATMEL_BASE_USART0	0xfffb0000
-#define ATMEL_BASE_USART1	0xfffb4000
-#define ATMEL_BASE_USART2	0xfffb8000
-#define ATMEL_BASE_SSC0		0xfffbc000
-#define ATMEL_BASE_ISI0		0xfffc0000
-#define ATMEL_BASE_EMAC0	0xfffc4000
-#define ATMEL_BASE_SPI0		0xfffc8000
-#define ATMEL_BASE_SPI1		0xfffcc000
-#define ATMEL_BASE_USART3	0xfffd0000
-#define ATMEL_BASE_USART4	0xfffd4000
-/* USART5 or TWI1:		0xfffd8000 */
-#define ATMEL_BASE_TCB1		0xfffdc000
-#define ATMEL_BASE_TC3		0xfffdc000
-#define ATMEL_BASE_TC4		0xfffdc040
-#define ATMEL_BASE_TC5		0xfffdc080
-#define ATMEL_BASE_ADC		0xfffe0000
-/* Reserved:	0xfffe4000 - 0xffffe7ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS		0xffffe800
-#define ATMEL_BASE_SDRAMC	0xffffea00
-#define ATMEL_BASE_SMC		0xffffec00
-#define ATMEL_BASE_MATRIX	0xffffee00
-#define ATMEL_BASE_CCFG         0xffffef14
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_DBGU		0xfffff200
-#define ATMEL_BASE_PIOA		0xfffff400
-#define ATMEL_BASE_PIOB		0xfffff600
-#define ATMEL_BASE_PIOC		0xfffff800
-/* EEFC:			0xfffffa00 */
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWN	0xfffffd10
-#define ATMEL_BASE_RTT		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-/* GPBR(non-XE SoCs):		0xfffffd50 */
-/* GPBR(XE SoCs):		0xfffffd60 */
-/* Reserved:	0xfffffd70 - 0xffffffff */
-
-/*
- * Internal Memory common on all these SoCs
- */
-#define ATMEL_BASE_BOOT		0x00000000	/* Boot mapped area */
-#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
-/* SRAM or FLASH:		0x00200000 */
-/* SRAM:			0x00300000 */
-/* Reserved:			0x00400000 */
-#define ATMEL_UHP_BASE		0x00500000	/* USB Host controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
-#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
-#define ATMEL_BASE_CS2		0x30000000
-#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
-#define ATMEL_BASE_CS4		0x50000000
-#define ATMEL_BASE_CS5		0x60000000
-#define ATMEL_BASE_CS6		0x70000000
-#define ATMEL_BASE_CS7		0x80000000
-
-/*
- * Other misc defines
- */
-#ifndef CONFIG_DM_GPIO
-#define ATMEL_PIO_PORTS		3		/* these SoCs have 3 PIO */
-#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
-#endif
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-
-/*
- * SoC specific defines
- */
-#if defined(CONFIG_AT91SAM9XE)
-# define ATMEL_CPU_NAME		"AT91SAM9XE"
-# define ATMEL_ID_TWI1		25	/* TWI 1 */
-# define ATMEL_BASE_FLASH	0x00200000	/* Internal FLASH */
-# define ATMEL_BASE_SRAM	0x00300000	/* Internal SRAM */
-# define ATMEL_BASE_TWI1	0xfffd8000
-# define ATMEL_BASE_EEFC	0xfffffa00
-# define ATMEL_BASE_GPBR	0xfffffd60
-#elif defined(CONFIG_AT91SAM9260)
-# define ATMEL_CPU_NAME		"AT91SAM9260"
-# define ATMEL_ID_USART5	25	/* USART 5 */
-# define ATMEL_BASE_SRAM0	0x00200000	/* Internal SRAM 0 */
-# define ATMEL_BASE_SRAM1	0x00300000	/* Internal SRAM 1 */
-# define ATMEL_BASE_USART5	0xfffd8000
-# define ATMEL_BASE_GPBR	0xfffffd50
-#elif defined(CONFIG_AT91SAM9G20)
-# define ATMEL_CPU_NAME		"AT91SAM9G20"
-# define ATMEL_ID_USART5	25	/* USART 5 */
-# define ATMEL_BASE_SRAM0	0x00200000	/* Internal SRAM 0 */
-# define ATMEL_BASE_SRAM1	0x00300000	/* Internal SRAM 1 */
-# define ATMEL_BASE_USART5	0xfffd8000
-# define ATMEL_BASE_GPBR	0xfffffd50
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
deleted file mode 100644
index dc61f48f52..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9260 datasheet revision B.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9260_MATRIX_H
-#define AT91SAM9260_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * This struct defines access to the matrix' maximum of
- * 16 masters and 16 slaves.
- * However, on the AT91SAM9260/9G20/9XE there exist only
- * 6 Masters and 5 Slaves!
- */
-struct at91_matrix {
-	u32	mcfg[16];	/* Master Configuration Registers */
-	u32	scfg[16];	/* Slave Configuration Registers */
-	u32	pras[16][2];	/* Priority Assignment Slave Registers */
-	u32	mrcr;		/* Master Remap Control Register */
-	u32	filler[0x06];
-	u32	ebicsa;		/* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT		0
-#define AT91_MATRIX_M1PR_SHIFT		4
-#define AT91_MATRIX_M2PR_SHIFT		8
-#define AT91_MATRIX_M3PR_SHIFT		12
-#define AT91_MATRIX_M4PR_SHIFT		16
-#define AT91_MATRIX_M5PR_SHIFT		20
-
-#define AT91_MATRIX_RCB0		(1 << 0)
-#define AT91_MATRIX_RCB1		(1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define AT91_MATRIX_DBPUC		(1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-#define AT91_MATRIX_EBI_IOSR_SEL	(1 << 17)
-
-/* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_SLOT_CYCLE		(0xff << 0)
-#define AT91_MATRIX_SLOT_CYCLE_(x)	(x << 0)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h
deleted file mode 100644
index 6dfcf4c0c8..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9261.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
- *
- * Copyright (C) SAN People
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoCs:
- * AT91SAM9261, AT91SAM9G10
- *
- * Note that those SoCs are mostly software and pin compatible,
- * therefore this file applies to all of them. Differences between
- * those SoCs are concentrated at the end of this file.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Peripherals */
-#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
-#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
-/* Reserved:		5 */
-#define ATMEL_ID_USART0	6	/* USART 0 */
-#define ATMEL_ID_USART1	7	/* USART 1 */
-#define ATMEL_ID_USART2	8	/* USART 2 */
-#define ATMEL_ID_MCI	9	/* Multimedia Card Interface */
-#define ATMEL_ID_UDP	10	/* USB Device Port */
-#define ATMEL_ID_TWI0	11	/* Two-Wire Interface 0 */
-#define ATMEL_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define ATMEL_ID_SSC2	16	/* Serial Synchronous Controller 2 */
-#define ATMEL_ID_TC0	17	/* Timer Counter 0 */
-#define ATMEL_ID_TC1	18	/* Timer Counter 1 */
-#define ATMEL_ID_TC2	19	/* Timer Counter 2 */
-#define ATMEL_ID_UHP	20	/* USB Host port */
-#define ATMEL_ID_LCDC	21	/* LDC Controller */
-/* Reserved:		22-28 */
-#define ATMEL_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define ATMEL_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_TCB0		0xfffa0000
-#define ATMEL_BASE_TC0		0xfffa0000
-#define ATMEL_BASE_TC1		0xfffa0040
-#define ATMEL_BASE_TC2		0xfffa0080
-#define ATMEL_BASE_UDP0		0xfffa4000
-#define ATMEL_BASE_MCI		0xfffa8000
-#define ATMEL_BASE_TWI0		0xfffac000
-#define ATMEL_BASE_USART0	0xfffb0000
-#define ATMEL_BASE_USART1	0xfffb4000
-#define ATMEL_BASE_USART2	0xfffb8000
-#define ATMEL_BASE_SSC0		0xfffbc000
-#define ATMEL_BASE_SSC1		0xfffc0000
-#define ATMEL_BASE_SSC2		0xfffc4000
-#define ATMEL_BASE_SPI0		0xfffc8000
-#define ATMEL_BASE_SPI1		0xfffcc000
-/* Reserved:	0xfffc4000 - 0xffffe9ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS		0xffffea00
-#define ATMEL_BASE_SDRAMC	0xffffea00
-#define ATMEL_BASE_SMC		0xffffec00
-#define ATMEL_BASE_MATRIX	0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_DBGU		0xfffff200
-#define ATMEL_BASE_PIOA		0xfffff400
-#define ATMEL_BASE_PIOB		0xfffff600
-#define ATMEL_BASE_PIOC		0xfffff800
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWN	0xfffffd10
-#define ATMEL_BASE_RTT		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-#define ATMEL_BASE_GPBR		0xfffffd50
-
-/*
- * Internal Memory common on all these SoCs
- */
-#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
-#define ATMEL_SIZE_SRAM		0x00028000	/* Internal SRAM size (160Kb) */
-
-#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
-#define ATMEL_SIZE_ROM		0x00008000	/* Internal ROM size (32Kb) */
-
-#define ATMEL_BASE_UHP		0x00500000	/* USB Host controller */
-#define ATMEL_BASE_LCDC		0x00600000	/* LDC controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
-#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
-#define ATMEL_BASE_CS2		0x30000000
-#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
-#define ATMEL_BASE_CS4		0x50000000
-#define ATMEL_BASE_CS5		0x60000000
-#define ATMEL_BASE_CS6		0x70000000
-#define ATMEL_BASE_CS7		0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		3		/* theese SoCs have 3 PIO */
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
-
-/*
- * SoC specific defines
- */
-#if defined(CONFIG_AT91SAM9261)
-# define ATMEL_CPU_NAME		"AT91SAM9261"
-#elif defined(CONFIG_AT91SAM9G10)
-# define ATMEL_CPU_NAME		"AT91SAM9G10"
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
deleted file mode 100644
index fc5f0831b8..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h]
- *
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9261_MATRIX_H
-#define AT91SAM9261_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
-	u32	mcfg;	/* Master Configuration Registers */
-	u32	scfg[5];	/* Slave Configuration Registers */
-	u32	filler[6];
-	u32	ebicsa;		/* EBI Chip Select Assignment Register */
-};
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT          0
-#define AT91_MATRIX_M1PR_SHIFT          4
-#define AT91_MATRIX_M2PR_SHIFT          8
-#define AT91_MATRIX_M3PR_SHIFT          12
-#define AT91_MATRIX_M4PR_SHIFT          16
-#define AT91_MATRIX_M5PR_SHIFT          20
-
-#define AT91_MATRIX_RCB0                (1 << 0)
-#define AT91_MATRIX_RCB1                (1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define AT91_MATRIX_DBPUC               (1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h
deleted file mode 100644
index 64a3888e22..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9263.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
- *
- * (C) 2007 Atmel Corporation.
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * Definitions for the SoC:
- * AT91SAM9263
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Peripherals */
-#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
-#define ATMEL_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */
-/* Reserved:		5 */
-/* Reserved:		6 */
-#define ATMEL_ID_USART0	7	/* USART 0 */
-#define ATMEL_ID_USART1	8	/* USART 1 */
-#define ATMEL_ID_USART2	9	/* USART 2 */
-#define ATMEL_ID_MCI0	10	/* Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1	11	/* Multimedia Card Interface 1 */
-#define ATMEL_ID_CAN	12	/* CAN */
-#define ATMEL_ID_TWI	13	/* Two-Wire Interface */
-#define ATMEL_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0	16	/* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1	17	/* Serial Synchronous Controller 1 */
-#define ATMEL_ID_AC97C	18	/* AC97 Controller */
-#define ATMEL_ID_TCB	19	/* Timer Counter 0, 1 and 2 */
-#define ATMEL_ID_PWMC	20	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_EMAC	21	/* Ethernet */
-/* Reserved:		22 */
-#define ATMEL_ID_2DGE	23	/* 2D Graphic Engine */
-#define ATMEL_ID_UDP	24	/* USB Device Port */
-#define ATMEL_ID_ISI	25	/* Image Sensor Interface */
-#define ATMEL_ID_LCDC	26	/* LCD Controller */
-#define ATMEL_ID_DMA	27	/* DMA Controller */
-/* Reserved:		28 */
-#define ATMEL_ID_UHP	29	/* USB Host port */
-#define ATMEL_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */
-#define ATMEL_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_UDP		0xfff78000
-#define ATMEL_BASE_TCB0		0xfff7c000
-#define ATMEL_BASE_TC0		0xfff7c000
-#define ATMEL_BASE_TC1		0xfff7c040
-#define ATMEL_BASE_TC2		0xfff7c080
-#define ATMEL_BASE_MCI0		0xfff80000
-#define ATMEL_BASE_MCI1		0xfff84000
-#define ATMEL_BASE_TWI		0xfff88000
-#define ATMEL_BASE_USART0	0xfff8c000
-#define ATMEL_BASE_USART1	0xfff90000
-#define ATMEL_BASE_USART2	0xfff94000
-#define ATMEL_BASE_SSC0		0xfff98000
-#define ATMEL_BASE_SSC1		0xfff9c000
-#define ATMEL_BASE_AC97C	0xfffa0000
-#define ATMEL_BASE_SPI0		0xfffa4000
-#define ATMEL_BASE_SPI1		0xfffa8000
-#define ATMEL_BASE_CAN		0xfffac000
-#define ATMEL_BASE_PWMC		0xfffb8000
-#define ATMEL_BASE_EMAC		0xfffbc000
-#define ATMEL_BASE_ISI		0xfffc4000
-#define ATMEL_BASE_2DGE		0xfffc8000
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_ECC0		0xffffe000
-#define ATMEL_BASE_SDRAMC0	0xffffe200
-#define ATMEL_BASE_SMC0		0xffffe400
-#define ATMEL_BASE_ECC1		0xffffe600
-#define ATMEL_BASE_SDRAMC1	0xffffe800
-#define ATMEL_BASE_SMC1		0xffffea00
-#define ATMEL_BASE_MATRIX	0xffffec00
-#define ATMEL_BASE_CCFG		0xffffed10
-#define ATMEL_BASE_DBGU		0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_PIOA		0xfffff200
-#define ATMEL_BASE_PIOB		0xfffff400
-#define ATMEL_BASE_PIOC		0xfffff600
-#define ATMEL_BASE_PIOD		0xfffff800
-#define ATMEL_BASE_PIOE		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWC	0xfffffd10
-#define ATMEL_BASE_RTT0		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-#define ATMEL_BASE_RTT1		0xfffffd50
-#define ATMEL_BASE_GPBR		0xfffffd60
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM 0 */
-
-#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM */
-
-#define ATMEL_BASE_SRAM1	0x00500000	/* Internal SRAM 1 */
-
-#define ATMEL_BASE_LCDC		0x00700000	/* LCD Controller */
-#define ATMEL_BASE_DMAC		0x00800000	/* DMA Controller */
-#define ATMEL_BASE_UHP		0x00a00000	/* USB Host controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
-#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
-#define ATMEL_BASE_CS2		0x30000000
-#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
-#define ATMEL_BASE_CS4		0x50000000
-#define ATMEL_BASE_CS5		0x60000000
-#define ATMEL_BASE_CS6		0x70000000
-#define ATMEL_BASE_CS7		0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
-#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME		"AT91SAM9263"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
deleted file mode 100644
index 54d862287b..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
- *
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9263_MATRIX_H
-#define AT91SAM9263_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * This struct defines access to the matrix' maximum of
- * 16 masters and 16 slaves.
- * Note: not all masters/slaves are available
- */
-struct at91_matrix {
-	u32	mcfg[16];	/* Master Configuration Registers */
-	u32	scfg[16];	/* Slave Configuration Registers */
-	u32	pras[16][2];	/* Priority Assignment Slave Registers */
-	u32	mrcr;		/* Master Remap Control Register */
-	u32	filler[0x06];
-	u32	ebicsa;		/* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT		0
-#define AT91_MATRIX_M1PR_SHIFT		4
-#define AT91_MATRIX_M2PR_SHIFT		8
-#define AT91_MATRIX_M3PR_SHIFT		12
-#define AT91_MATRIX_M4PR_SHIFT		16
-#define AT91_MATRIX_M5PR_SHIFT		20
-
-#define AT91_MATRIX_RCB0		(1 << 0)
-#define AT91_MATRIX_RCB1		(1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define AT91_MATRIX_DBPUC		(1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
deleted file mode 100644
index d0bf0c2e2b..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
-#define __ASM_ARCH_AT91SAM9_MATRIX_H
-
-#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#include <asm/arch/at91sam9260_matrix.h>
-#elif defined(CONFIG_AT91SAM9261)
-#include <asm/arch/at91sam9261_matrix.h>
-#elif defined(CONFIG_AT91SAM9263)
-#include <asm/arch/at91sam9263_matrix.h>
-#elif defined(CONFIG_AT91SAM9RL)
-#include <asm/arch/at91sam9rl_matrix.h>
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-#include <asm/arch/at91sam9g45_matrix.h>
-#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
-#include <asm/arch/at91sam9x5_matrix.h>
-#else
-#error "Unsupported AT91SAM9/CAP9 processor"
-#endif
-
-#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
deleted file mode 100644
index 3a076c6b80..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
- *
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * SDRAM Controllers (SDRAMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM9_SDRAMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef ATMEL_BASE_SDRAMC
-#define ATMEL_BASE_SDRAMC	ATMEL_BASE_SDRAMC0
-#endif
-
-#define AT91_ASM_SDRAMC_MR	ATMEL_BASE_SDRAMC
-#define AT91_ASM_SDRAMC_TR	(ATMEL_BASE_SDRAMC + 0x04)
-#define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
-#define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
-
-#else
-struct sdramc_reg {
-	u32	mr;
-	u32	tr;
-	u32	cr;
-	u32	lpr;
-	u32	ier;
-	u32	idr;
-	u32	imr;
-	u32	isr;
-	u32	mdr;
-};
-
-int sdramc_initialize(unsigned int sdram_address,
-		      const struct sdramc_reg *p);
-#endif
-
-/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR		(ATMEL_BASE_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
-#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
-#define			AT91_SDRAMC_MODE_NORMAL		0
-#define			AT91_SDRAMC_MODE_NOP		1
-#define			AT91_SDRAMC_MODE_PRECHARGE	2
-#define			AT91_SDRAMC_MODE_LMR		3
-#define			AT91_SDRAMC_MODE_REFRESH	4
-#define			AT91_SDRAMC_MODE_EXT_LMR	5
-#define			AT91_SDRAMC_MODE_DEEP		6
-
-#define AT91_SDRAMC_TR		(ATMEL_BASE_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
-#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
-
-#define AT91_SDRAMC_CR		(ATMEL_BASE_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
-#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
-#define			AT91_SDRAMC_NC_8	(0 << 0)
-#define			AT91_SDRAMC_NC_9	(1 << 0)
-#define			AT91_SDRAMC_NC_10	(2 << 0)
-#define			AT91_SDRAMC_NC_11	(3 << 0)
-#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
-#define			AT91_SDRAMC_NR_11	(0 << 2)
-#define			AT91_SDRAMC_NR_12	(1 << 2)
-#define			AT91_SDRAMC_NR_13	(2 << 2)
-#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
-#define			AT91_SDRAMC_NB_2	(0 << 4)
-#define			AT91_SDRAMC_NB_4	(1 << 4)
-#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
-#define			AT91_SDRAMC_CAS_1	(1 << 5)
-#define			AT91_SDRAMC_CAS_2	(2 << 5)
-#define			AT91_SDRAMC_CAS_3	(3 << 5)
-#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
-#define			AT91_SDRAMC_DBW_32	(0 << 7)
-#define			AT91_SDRAMC_DBW_16	(1 << 7)
-#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
-#define		AT91_SDRAMC_TWR_VAL(x)	(x << 8)
-#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
-#define			AT91_SDRAMC_TRC_VAL(x)	(x << 12)
-#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
-#define		AT91_SDRAMC_TRP_VAL(x)	(x << 16)
-#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
-#define			AT91_SDRAMC_TRCD_VAL(x)	(x << 20)
-#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
-#define		AT91_SDRAMC_TRAS_VAL(x)	(x << 24)
-#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
-#define		AT91_SDRAMC_TXSR_VAL(x)	(x << 28)
-
-#define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
-#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
-#define			AT91_SDRAMC_LPCB_DISABLE		0
-#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
-#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
-#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
-#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
-#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
-#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
-#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
-#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
-#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
-#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
-
-#define AT91_SDRAMC_IER		(ATMEL_BASE_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR		(ATMEL_BASE_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR		(ATMEL_BASE_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR		(ATMEL_BASE_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
-#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
-
-#define AT91_SDRAMC_MDR		(ATMEL_BASE_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
-#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
-#define			AT91_SDRAMC_MD_SDRAM		0
-#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
deleted file mode 100644
index d29e98e711..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
- *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on AT91SAM9261 datasheet revision D.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9_SMC_H
-#define AT91SAM9_SMC_H
-
-#ifdef __ASSEMBLY__
-
-#ifndef ATMEL_BASE_SMC
-#define ATMEL_BASE_SMC	ATMEL_BASE_SMC0
-#endif
-
-#define AT91_ASM_SMC_SETUP0	ATMEL_BASE_SMC
-#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x04)
-#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x08)
-#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x0C)
-
-#else
-
-typedef struct	at91_cs {
-	u32	setup;		/* 0x00 SMC Setup Register */
-	u32	pulse;		/* 0x04 SMC Pulse Register */
-	u32	cycle;		/* 0x08 SMC Cycle Register */
-	u32	mode;		/* 0x0C SMC Mode Register */
-} at91_cs_t;
-
-typedef struct	at91_smc {
-	at91_cs_t	cs[8];
-} at91_smc_t;
-
-#endif /*  __ASSEMBLY__ */
-
-#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
-#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
-#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
-#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
-
-#define AT91_SMC_PULSE_NWE(x)		(x & 0x7f)
-#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x7f) << 8)
-#define AT91_SMC_PULSE_NRD(x)		((x & 0x7f) << 16)
-#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x7f) << 24)
-
-#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
-#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
-
-#define AT91_SMC_MODE_RM_NCS		0x00000000
-#define AT91_SMC_MODE_RM_NRD		0x00000001
-#define AT91_SMC_MODE_WM_NCS		0x00000000
-#define AT91_SMC_MODE_WM_NWE		0x00000002
-
-#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
-#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
-#define AT91_SMC_MODE_EXNW_READY	0x00000030
-
-#define AT91_SMC_MODE_BAT		0x00000100
-#define AT91_SMC_MODE_DBW_8		0x00000000
-#define AT91_SMC_MODE_DBW_16		0x00001000
-#define AT91_SMC_MODE_DBW_32		0x00002000
-#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
-#define AT91_SMC_MODE_TDF		0x00100000
-#define AT91_SMC_MODE_PMEN		0x01000000
-#define AT91_SMC_MODE_PS_4		0x00000000
-#define AT91_SMC_MODE_PS_8		0x10000000
-#define AT91_SMC_MODE_PS_16		0x20000000
-#define AT91_SMC_MODE_PS_32		0x30000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h
deleted file mode 100644
index 6df8cdb56d..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9g45.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9M1x family
- *
- * (C) 2008 Atmel Corporation.
- *
- * Definitions for the SoC:
- * AT91SAM9G45
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
-#define ATMEL_ID_PIOA	2	/* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC	4	/* Parallel I/O Controller C */
-#define ATMEL_ID_PIODE	5	/* Parallel I/O Controller D and E */
-#define ATMEL_ID_TRNG	6	/* True Random Number Generator */
-#define ATMEL_ID_USART0	7	/* USART 0 */
-#define ATMEL_ID_USART1	8	/* USART 1 */
-#define ATMEL_ID_USART2	9	/* USART 2 */
-#define ATMEL_ID_USART3	10	/* USART 3 */
-#define ATMEL_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_TWI0	12	/* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1	13	/* Two-Wire Interface 1 */
-#define ATMEL_ID_SPI0	14	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	15	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SSC0	16	/* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1	17	/* Synchronous Serial Controller 1 */
-#define ATMEL_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC	20	/* Touch Screen ADC Controller */
-#define ATMEL_ID_DMA	21	/* DMA Controller */
-#define ATMEL_ID_UHPHS	22	/* USB Host High Speed */
-#define ATMEL_ID_LCDC	23	/* LCD Controller */
-#define ATMEL_ID_AC97C	24	/* AC97 Controller */
-#define ATMEL_ID_EMAC	25	/* Ethernet MAC */
-#define ATMEL_ID_ISI	26	/* Image Sensor Interface */
-#define ATMEL_ID_UDPHS	27	/* USB Device High Speed */
-#define ATMEL_ID_AESTDESSHA 28	/* AES + T-DES + SHA */
-#define ATMEL_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_VDEC	30	/* Video Decoder */
-#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_UDPHS	0xfff78000
-#define ATMEL_BASE_TC0		0xfff7c000
-#define ATMEL_BASE_TC1		0xfff7c040
-#define ATMEL_BASE_TC2		0xfff7c080
-#define ATMEL_BASE_MCI0		0xfff80000
-#define ATMEL_BASE_TWI0		0xfff84000
-#define ATMEL_BASE_TWI1		0xfff88000
-#define ATMEL_BASE_USART0	0xfff8c000
-#define ATMEL_BASE_USART1	0xfff90000
-#define ATMEL_BASE_USART2	0xfff94000
-#define ATMEL_BASE_USART3	0xfff98000
-#define ATMEL_BASE_SSC0		0xfff9c000
-#define ATMEL_BASE_SSC1		0xfffa0000
-#define ATMEL_BASE_SPI0		0xfffa4000
-#define ATMEL_BASE_SPI1		0xfffa8000
-#define ATMEL_BASE_AC97C	0xfffac000
-#define ATMEL_BASE_TSC		0xfffb0000
-#define ATMEL_BASE_ISI		0xfffb4000
-#define ATMEL_BASE_PWMC		0xfffb8000
-#define ATMEL_BASE_EMAC		0xfffbc000
-#define ATMEL_BASE_AES		0xfffc0000
-#define ATMEL_BASE_TDES		0xfffc4000
-#define ATMEL_BASE_SHA		0xfffc8000
-#define ATMEL_BASE_TRNG		0xfffcc000
-#define ATMEL_BASE_MCI1		0xfffd0000
-#define ATMEL_BASE_TC3		0xfffd4000
-#define ATMEL_BASE_TC4		0xfffd4040
-#define ATMEL_BASE_TC5		0xfffd4080
-/* Reserved:	0xfffd8000 - 0xffffe1ff */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS		0xffffe200
-#define ATMEL_BASE_ECC		0xffffe200
-#define ATMEL_BASE_DDRSDRC1	0xffffe400
-#define ATMEL_BASE_DDRSDRC0	0xffffe600
-#define ATMEL_BASE_SMC		0xffffe800
-#define ATMEL_BASE_MATRIX	0xffffea00
-#define ATMEL_BASE_DMA		0xffffec00
-#define ATMEL_BASE_DBGU		0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_PIOA		0xfffff200
-#define ATMEL_BASE_PIOB		0xfffff400
-#define ATMEL_BASE_PIOC		0xfffff600
-#define ATMEL_BASE_PIOD		0xfffff800
-#define ATMEL_BASE_PIOE		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWN	0xfffffd10
-#define ATMEL_BASE_RTT		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-#define ATMEL_BASE_GPBR		0xfffffd60
-#define ATMEL_BASE_RTC		0xfffffdb0
-/* Reserved:	0xfffffdc0 - 0xffffffff */
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
-#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
-#define ATMEL_BASE_LCDC		0x00500000	/* LCD Controller */
-#define ATMEL_BASE_UDPHS_FIFO	0x00600000	/* USB Device HS controller */
-#define ATMEL_BASE_HCI		0x00700000	/* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI		0x00800000	/* USB Host controller (EHCI) */
-#define ATMEL_BASE_VDEC		0x00900000	/* Video Decoder Controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000
-#define ATMEL_BASE_CS1		0x20000000
-#define ATMEL_BASE_CS2		0x30000000
-#define ATMEL_BASE_CS3		0x40000000
-#define ATMEL_BASE_CS4		0x50000000
-#define ATMEL_BASE_CS5		0x60000000
-#define ATMEL_BASE_CS6		0x70000000
-#define ATMEL_BASE_CS7		0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		5		/* this SoCs has 5 PIO */
-#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME		"AT91SAM9G45"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
deleted file mode 100644
index 80e49e3430..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9M1x family
- *
- *  Copyright (C) 2008 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef AT91SAM9G45_MATRIX_H
-#define AT91SAM9G45_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
-	u32	mcfg[16];
-	u32	scfg[16];
-	u32	pras[16][2];
-	u32	mrcr;           /* 0x100 Master Remap Control */
-	u32	filler[3];
-	u32	tcmr;
-	u32	filler2;
-	u32	ddrmpr;
-	u32	filler3[3];
-	u32	ebicsa;
-	u32	filler4[47];
-	u32	wpmr;
-	u32	wpsr;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define	AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define	AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define	AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define	AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define	AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define	AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define	AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define	AT91_MATRIX_ULBT_128		(7 << 0)
-
-#define	AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define	AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define	AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-
-#define AT91_MATRIX_M0PR_SHIFT          0
-#define AT91_MATRIX_M1PR_SHIFT          4
-#define AT91_MATRIX_M2PR_SHIFT          8
-#define AT91_MATRIX_M3PR_SHIFT          12
-#define AT91_MATRIX_M4PR_SHIFT          16
-#define AT91_MATRIX_M5PR_SHIFT          20
-#define AT91_MATRIX_M6PR_SHIFT          24
-#define AT91_MATRIX_M7PR_SHIFT          28
-
-#define AT91_MATRIX_M8PR_SHIFT          0  /* register B */
-#define AT91_MATRIX_M9PR_SHIFT          4  /* register B */
-#define AT91_MATRIX_M10PR_SHIFT         8  /* register B */
-#define AT91_MATRIX_M11PR_SHIFT         12 /* register B */
-
-#define AT91_MATRIX_RCB0                (1 << 0)
-#define AT91_MATRIX_RCB1                (1 << 1)
-#define AT91_MATRIX_RCB2                (1 << 2)
-#define AT91_MATRIX_RCB3                (1 << 3)
-#define AT91_MATRIX_RCB4                (1 << 4)
-#define AT91_MATRIX_RCB5                (1 << 5)
-#define AT91_MATRIX_RCB6                (1 << 6)
-#define AT91_MATRIX_RCB7                (1 << 7)
-#define AT91_MATRIX_RCB8                (1 << 8)
-#define AT91_MATRIX_RCB9                (1 << 9)
-#define AT91_MATRIX_RCB10               (1 << 10)
-
-#define AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
-#define AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
-#define AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
-#define AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h
deleted file mode 100644
index 3a8e6d62ce..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl.h]
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Peripherals */
-#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
-#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
-#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
-#define ATMEL_ID_PIOD	5	/* Parallel IO Controller D */
-#define ATMEL_ID_USART0	6	/* USART 0 */
-#define ATMEL_ID_USART1	7	/* USART 1 */
-#define ATMEL_ID_USART2	8	/* USART 2 */
-#define ATMEL_ID_USART3	9	/* USART 3 */
-#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
-#define ATMEL_ID_TWI0	11	/* TWI 0 */
-#define ATMEL_ID_TWI1	12	/* TWI 1 */
-#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
-#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define ATMEL_ID_TC0	16	/* Timer Counter 0 */
-#define ATMEL_ID_TC1	17	/* Timer Counter 1 */
-#define ATMEL_ID_TC2	18	/* Timer Counter 2 */
-#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC	20	/* Touch Screen Controller */
-#define ATMEL_ID_DMA	21	/* DMA Controller */
-#define ATMEL_ID_UDPHS	22	/* USB Device HS */
-#define ATMEL_ID_LCDC	23	/* LCD Controller */
-#define ATMEL_ID_AC97C	24	/* AC97 Controller */
-#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define ATMEL_BASE_TCB0		0xfffa0000
-#define ATMEL_BASE_TC0		0xfffa0000
-#define ATMEL_BASE_TC1		0xfffa0040
-#define ATMEL_BASE_TC2		0xfffa0080
-#define ATMEL_BASE_MCI		0xfffa4000
-#define ATMEL_BASE_TWI0		0xfffa8000
-#define ATMEL_BASE_TWI1		0xfffac000
-#define ATMEL_BASE_USART0	0xfffb0000
-#define ATMEL_BASE_USART1	0xfffb4000
-#define ATMEL_BASE_USART2	0xfffb8000
-#define ATMEL_BASE_USART3	0xfffbc000
-#define ATMEL_BASE_SSC0		0xfffc0000
-#define ATMEL_BASE_SSC1		0xfffc4000
-#define ATMEL_BASE_PWMC		0xfffc8000
-#define ATMEL_BASE_SPI0		0xfffcc000
-#define ATMEL_BASE_TSC		0xfffd0000
-#define ATMEL_BASE_UDPHS	0xfffd4000
-#define ATMEL_BASE_AC97C	0xfffd8000
-#define ATMEL_BASE_SYS		0xffffc000
-
-/*
- * System Peripherals
- */
-#define ATMEL_BASE_DMA		0xffffe600
-#define ATMEL_BASE_ECC		0xffffe800
-#define ATMEL_BASE_SDRAMC	0xffffea00
-#define ATMEL_BASE_SMC		0xffffec00
-#define ATMEL_BASE_MATRIX	0xffffee00
-#define ATMEL_BASE_CCFG		0xffffef10
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_DBGU		0xfffff200
-#define ATMEL_BASE_PIOA		0xfffff400
-#define ATMEL_BASE_PIOB		0xfffff600
-#define ATMEL_BASE_PIOC		0xfffff800
-#define ATMEL_BASE_PIOD		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffd00
-#define ATMEL_BASE_SHDWC	0xfffffd10
-#define ATMEL_BASE_RTT		0xfffffd20
-#define ATMEL_BASE_PIT		0xfffffd30
-#define ATMEL_BASE_WDT		0xfffffd40
-#define ATMEL_BASE_SCKCR	0xfffffd50
-#define ATMEL_BASE_GPBR		0xfffffd60
-#define ATMEL_BASE_RTC		0xfffffe00
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
-#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
-
-#define ATMEL_BASE_LCDC		0x00500000	/* LCD Controller */
-#define ATMEL_UHP_BASE		0x00600000	/* USB Device HS controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000
-#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
-#define ATMEL_BASE_CS2		0x30000000
-#define ATMEL_BASE_CS3		0x40000000	/* NAND */
-#define ATMEL_BASE_CS4		0x50000000	/* Compact Flash Slot 0 */
-#define ATMEL_BASE_CS5		0x60000000	/* Compact Flash Slot 1 */
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		4		/* this SoC has 4 PIO */
-#define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
-
-/*
- * Cpu Name
- */
-#define ATMEL_CPU_NAME		"AT91SAM9RL"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
deleted file mode 100644
index 295f768b55..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9rl_matrix.h]
- *
- *  Copyright (C) 2007 Atmel Corporation
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_MATRIX_H
-#define AT91SAM9RL_MATRIX_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_matrix {
-	u32	mcfg[16];	/* Master Configuration Registers */
-	u32	scfg[16];	/* Slave Configuration Registers */
-	u32	pras[16][2];	/* Priority Assignment Slave Registers */
-	u32	mrcr;		/* Master Remap Control Register */
-	u32	filler[7];
-	u32	ebicsa;		/* EBI Chip Select Assignment Register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
-#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
-
-#define AT91_MATRIX_M0PR_SHIFT		0
-#define AT91_MATRIX_M1PR_SHIFT		4
-#define AT91_MATRIX_M2PR_SHIFT		8
-#define AT91_MATRIX_M3PR_SHIFT		12
-#define AT91_MATRIX_M4PR_SHIFT		16
-#define AT91_MATRIX_M5PR_SHIFT		20
-
-#define AT91_MATRIX_RCB0		(1 << 0)
-#define AT91_MATRIX_RCB1		(1 << 1)
-
-#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define AT91_MATRIX_DBPUC		(1 << 8)
-#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
deleted file mode 100644
index 36a5cdf476..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9x5 family
- *
- *  Copyright (C) 2012-2013 Atmel Corporation.
- *
- * Definitions for the SoC:
- * AT91SAM9x5 & AT91SAM9N12
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AT91SAM9X5_H__
-#define __AT91SAM9X5_H__
-
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 family */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
-#define ATMEL_ID_PIOAB	2	/* Parallel I/O Controller A and B */
-#define ATMEL_ID_PIOCD	3	/* Parallel I/O Controller C and D */
-#define ATMEL_ID_SMD	4	/* SMD Soft Modem (SMD), only for AT91SAM9X5 */
-#define ATMEL_ID_FUSE	4	/* FUSE Controller, only for AT91SAM9N12 */
-#define ATMEL_ID_USART0	5	/* USART 0 */
-#define ATMEL_ID_USART1	6	/* USART 1 */
-#define ATMEL_ID_USART2	7	/* USART 2 */
-#define ATMEL_ID_USART3	8	/* USART 3 */
-#define ATMEL_ID_TWI0	9	/* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1	10	/* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2	11	/* Two-Wire Interface 2 */
-#define ATMEL_ID_HSMCI0	12	/* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_SPI0	13	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	14	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_UART0	15	/* UART 0 */
-#define ATMEL_ID_UART1	16	/* UART 1 */
-#define ATMEL_ID_TC01	17	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define ATMEL_ID_PWM	18	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_ADC	19	/* ADC Controller */
-#define ATMEL_ID_DMAC0	20	/* DMA Controller 0 */
-#define ATMEL_ID_DMAC1	21	/* DMA Controller 1 */
-#define ATMEL_ID_UHPHS	22	/* USB Host High Speed */
-#define ATMEL_ID_UDPHS	23	/* USB Device High Speed */
-#define ATMEL_ID_EMAC0	24	/* Ethernet MAC0 */
-#define ATMEL_ID_LCDC	25	/* LCD Controller */
-#define ATMEL_ID_HSMCI1	26	/* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_EMAC1	27	/* Ethernet MAC1 */
-#define ATMEL_ID_SSC	28	/* Synchronous Serial Controller */
-#define ATMEL_ID_TRNG	30	/* True Random Number Generator */
-#define ATMEL_ID_IRQ	31	/* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define ATMEL_BASE_SPI0		0xf0000000
-#define ATMEL_BASE_SPI1		0xf0004000
-#define ATMEL_BASE_HSMCI0	0xf0008000
-#define ATMEL_BASE_HSMCI1	0xf000c000
-#define ATMEL_BASE_SSC		0xf0010000
-#define ATMEL_BASE_CAN0		0xf8000000
-#define ATMEL_BASE_CAN1		0xf8004000
-#define ATMEL_BASE_TC0		0xf8008000
-#define ATMEL_BASE_TC1		0xf8008040
-#define ATMEL_BASE_TC2		0xf8008080
-#define ATMEL_BASE_TC3		0xf800c000
-#define ATMEL_BASE_TC4		0xf800c040
-#define ATMEL_BASE_TC5		0xf800c080
-#define ATMEL_BASE_TWI0		0xf8010000
-#define ATMEL_BASE_TWI1		0xf8014000
-#define ATMEL_BASE_TWI2		0xf8018000
-#define ATMEL_BASE_USART0	0xf801c000
-#define ATMEL_BASE_USART1	0xf8020000
-#define ATMEL_BASE_USART2	0xf8024000
-#define ATMEL_BASE_USART3	0xf8028000
-#define ATMEL_BASE_EMAC0	0xf802c000
-#define ATMEL_BASE_EMAC1	0xf8030000
-#define ATMEL_BASE_PWM		0xf8034000
-#define ATMEL_BASE_LCDC		0xf8038000
-#define ATMEL_BASE_UDPHS	0xf803c000
-#define ATMEL_BASE_UART0	0xf8040000
-#define ATMEL_BASE_UART1	0xf8044000
-#define ATMEL_BASE_ISI		0xf8048000
-#define ATMEL_BASE_ADC		0xf804c000
-#define ATMEL_BASE_SYS		0xffffc000
-
-/*
- * System Peripherals
- */
-#define ATMEL_BASE_FUSE		0xffffdc00
-#define ATMEL_BASE_MATRIX	0xffffde00
-#define ATMEL_BASE_PMECC	0xffffe000
-#define ATMEL_BASE_PMERRLOC	0xffffe600
-#define ATMEL_BASE_DDRSDRC	0xffffe800
-#define ATMEL_BASE_SMC		0xffffea00
-#define ATMEL_BASE_DMAC0	0xffffec00
-#define ATMEL_BASE_DMAC1	0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_DBGU		0xfffff200
-#define ATMEL_BASE_PIOA		0xfffff400
-#define ATMEL_BASE_PIOB		0xfffff600
-#define ATMEL_BASE_PIOC		0xfffff800
-#define ATMEL_BASE_PIOD		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffe00
-#define ATMEL_BASE_SHDWC	0xfffffe10
-#define ATMEL_BASE_PIT		0xfffffe30
-#define ATMEL_BASE_WDT		0xfffffe40
-#define ATMEL_BASE_GPBR		0xfffffe60
-#define ATMEL_BASE_RTC		0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM		0x00100000 /* Internal ROM base address */
-#define ATMEL_BASE_SRAM		0x00300000 /* Internal SRAM base address */
-
-#ifdef CONFIG_AT91SAM9N12
-#define ATMEL_BASE_OHCI		0x00500000 /* USB Host controller */
-#else	/* AT91SAM9X5 */
-#define ATMEL_BASE_SMD		0x00400000 /* SMD Controller */
-#define ATMEL_BASE_UDPHS_FIFO	0x00500000 /* USB Device HS controller */
-#define ATMEL_BASE_OHCI		0x00600000 /* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI		0x00700000 /* USB Host controller (EHCI) */
-#endif
-
-/* 9x5 series chip id definitions */
-#define ARCH_ID_AT91SAM9X5	0x819a05a0
-#define ARCH_ID_VERSION_MASK	0x1f
-#define ARCH_EXID_AT91SAM9G15	0x00000000
-#define ARCH_EXID_AT91SAM9G35	0x00000001
-#define ARCH_EXID_AT91SAM9X35	0x00000002
-#define ARCH_EXID_AT91SAM9G25	0x00000003
-#define ARCH_EXID_AT91SAM9X25	0x00000004
-
-#define cpu_is_at91sam9x5()	(get_chip_id() == ARCH_ID_AT91SAM9X5)
-#define cpu_is_at91sam9g15()	(cpu_is_at91sam9x5() && \
-			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
-#define cpu_is_at91sam9g25()	(cpu_is_at91sam9x5() && \
-			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
-#define cpu_is_at91sam9g35()	(cpu_is_at91sam9x5() && \
-			(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
-#define cpu_is_at91sam9x25()	(cpu_is_at91sam9x5() && \
-			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
-#define cpu_is_at91sam9x35()	(cpu_is_at91sam9x5() && \
-			(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
-
-/*
- * Cpu Name
- */
-#ifdef CONFIG_AT91SAM9N12
-#define ATMEL_CPU_NAME	"AT91SAM9N12"
-#else	/* AT91SAM9X5 */
-#define ATMEL_CPU_NAME	get_cpu_name()
-#endif
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS         4
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV            (0x3fff <<  0)  /* Slow Clock Divider Mask */
-#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
-#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
-
-/*
- * PMECC table in ROM
- */
-#define ATMEL_PMECC_INDEX_OFFSET_512	0x8000
-#define ATMEL_PMECC_INDEX_OFFSET_1024	0x10000
-
-/*
- * at91sam9x5 specific prototypes
- */
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_emac1(void);
-unsigned int has_emac0(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
deleted file mode 100644
index bd0b25adc9..0000000000
--- a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Matrix-centric header file for the AT91SAM9X5 family
- *
- *  Copyright (C) 2012-2013 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AT91SAM9X5_MATRIX_H__
-#define __AT91SAM9X5_MATRIX_H__
-
-#ifndef __ASSEMBLY__
-
-/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
-struct at91_matrix {
-	u32	mcfg[16];
-	u32	scfg[16];
-	u32	pras[16][2];
-	u32	mrcr;           /* 0x100 Master Remap Control */
-	u32	filler[5];
-#ifdef CONFIG_AT91SAM9X5
-	u32	filler1[2];
-#endif
-	/* EBI Chip Select Assignment Register
-	 * 0x118: AT91SAM9N12
-	 * 0x120: AT91SAM9X5
-	 */
-	u32	ebicsa;
-	u32	filler4[47];
-#ifdef CONFIG_AT91SAM9N12
-	u32	filler5[2];
-#endif
-	u32	wpmr;
-	u32	wpsr;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
-#define AT91_MATRIX_ULBT_128		(7 << 0)
-
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
-
-#define AT91_MATRIX_M0PR_SHIFT          0
-#define AT91_MATRIX_M1PR_SHIFT          4
-#define AT91_MATRIX_M2PR_SHIFT          8
-#define AT91_MATRIX_M3PR_SHIFT          12
-#define AT91_MATRIX_M4PR_SHIFT          16
-#define AT91_MATRIX_M5PR_SHIFT          20
-#define AT91_MATRIX_M6PR_SHIFT          24
-#define AT91_MATRIX_M7PR_SHIFT          28
-
-#define AT91_MATRIX_M8PR_SHIFT          0  /* register B */
-#define AT91_MATRIX_M9PR_SHIFT          4  /* register B */
-#define AT91_MATRIX_M10PR_SHIFT         8  /* register B */
-#define AT91_MATRIX_M11PR_SHIFT         12 /* register B */
-
-#define AT91_MATRIX_RCB0                (1 << 0)
-#define AT91_MATRIX_RCB1                (1 << 1)
-#define AT91_MATRIX_RCB2                (1 << 2)
-#define AT91_MATRIX_RCB3                (1 << 3)
-#define AT91_MATRIX_RCB4                (1 << 4)
-#define AT91_MATRIX_RCB5                (1 << 5)
-#define AT91_MATRIX_RCB6                (1 << 6)
-#define AT91_MATRIX_RCB7                (1 << 7)
-#define AT91_MATRIX_RCB8                (1 << 8)
-#define AT91_MATRIX_RCB9                (1 << 9)
-#define AT91_MATRIX_RCB10               (1 << 10)
-
-#define AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
-#define AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
-#define AT91_MATRIX_EBI_DBPD_ON                 (0 << 9)
-#define AT91_MATRIX_EBI_DBPD_OFF                (1 << 9)
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
-#define AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
-#define AT91_MATRIX_MP_OFF                      (0 << 25)
-#define AT91_MATRIX_MP_ON                       (1 << 25)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
deleted file mode 100644
index 130a85abee..0000000000
--- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ATMEL_MPDDRC_H__
-#define __ATMEL_MPDDRC_H__
-
-/*
- * Only define the needed register in mpddr
- * If other register needed, will add them later
- */
-struct atmel_mpddr {
-	u32 mr;
-	u32 rtr;
-	u32 cr;
-	u32 tpr0;
-	u32 tpr1;
-	u32 tpr2;
-	u32 reserved[2];
-	u32 md;
-};
-
-int ddr2_init(const unsigned int ram_address,
-	       const struct atmel_mpddr *mpddr);
-
-/* Bit field in mode register */
-#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
-#define ATMEL_MPDDRC_MR_MODE_NOP_CMD		0x1
-#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD	0x2
-#define ATMEL_MPDDRC_MR_MODE_LMR_CMD		0x3
-#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD		0x4
-#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD	0x5
-#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD		0x6
-#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD		0x7
-
-/* Bit field in configuration register */
-#define ATMEL_MPDDRC_CR_NC_MASK			0x3
-#define ATMEL_MPDDRC_CR_NC_COL_9		0x0
-#define ATMEL_MPDDRC_CR_NC_COL_10		0x1
-#define ATMEL_MPDDRC_CR_NC_COL_11		0x2
-#define ATMEL_MPDDRC_CR_NC_COL_12		0x3
-#define ATMEL_MPDDRC_CR_NR_MASK			(0x3 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_11		(0x0 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_12		(0x1 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_13		(0x2 << 2)
-#define ATMEL_MPDDRC_CR_NR_ROW_14		(0x3 << 2)
-#define ATMEL_MPDDRC_CR_CAS_MASK		(0x7 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2		(0x2 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3		(0x3 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4		(0x4 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5		(0x5 << 4)
-#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6		(0x6 << 4)
-#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED	(0x1 << 7)
-#define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
-#define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
-#define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
-#define ATMEL_MPDDRC_CR_DQMS_SHARED		(0x1 << 16)
-#define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
-#define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
-#define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)
-#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED	(0x1 << 22)
-#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED		(0x1 << 23)
-
-/* Bit field in timing parameter 0 register */
-#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET		0
-#define ATMEL_MPDDRC_TPR0_TRAS_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET		4
-#define ATMEL_MPDDRC_TPR0_TRCD_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TWR_OFFSET		8
-#define ATMEL_MPDDRC_TPR0_TWR_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TRC_OFFSET		12
-#define ATMEL_MPDDRC_TPR0_TRC_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TRP_OFFSET		16
-#define ATMEL_MPDDRC_TPR0_TRP_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET		20
-#define ATMEL_MPDDRC_TPR0_TRRD_MASK		0xf
-#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET		24
-#define ATMEL_MPDDRC_TPR0_TWTR_MASK		0x7
-#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET	27
-#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK		0x1
-#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET		28
-#define ATMEL_MPDDRC_TPR0_TMRD_MASK		0xf
-
-/* Bit field in timing parameter 1 register */
-#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET		0
-#define ATMEL_MPDDRC_TPR1_TRFC_MASK		0x7f
-#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET		8
-#define ATMEL_MPDDRC_TPR1_TXSNR_MASK		0xff
-#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET		16
-#define ATMEL_MPDDRC_TPR1_TXSRD_MASK		0xff
-#define ATMEL_MPDDRC_TPR1_TXP_OFFSET		24
-#define ATMEL_MPDDRC_TPR1_TXP_MASK		0xf
-
-/* Bit field in timing parameter 2 register */
-#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET		0
-#define ATMEL_MPDDRC_TPR2_TXARD_MASK		0xf
-#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET		4
-#define ATMEL_MPDDRC_TPR2_TXARDS_MASK		0xf
-#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET		8
-#define ATMEL_MPDDRC_TPR2_TRPA_MASK		0xf
-#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET		12
-#define ATMEL_MPDDRC_TPR2_TRTP_MASK		0x7
-#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET		16
-#define ATMEL_MPDDRC_TPR2_TFAW_MASK		0xf
-
-/* Bit field in Memory Device Register */
-#define ATMEL_MPDDRC_MD_LPDDR_SDRAM	0x3
-#define ATMEL_MPDDRC_MD_DDR2_SDRAM	0x6
-#define ATMEL_MPDDRC_MD_DBW_MASK	(0x1 << 4)
-#define ATMEL_MPDDRC_MD_DBW_32_BITS	(0x0 << 4)
-#define ATMEL_MPDDRC_MD_DBW_16_BITS	(0x1 << 4)
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/include/asm/arch-at91/atmel_serial.h
deleted file mode 100644
index 5bc094b355..0000000000
--- a/arch/arm/include/asm/arch-at91/atmel_serial.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _ATMEL_SERIAL_H
-#define _ATMEL_SERIAL_H
-
-/* Information about a serial port */
-struct atmel_serial_platdata {
-	uint32_t base_addr;
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
deleted file mode 100644
index 38b5012fce..0000000000
--- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2005-2013 Atmel Corporation
- *			   Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ATMEL_USBA_UDC_H__
-#define __ATMEL_USBA_UDC_H__
-
-#include <linux/usb/atmel_usba_udc.h>
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)		\
-	[idx] = {					\
-		.name	= nam,				\
-		.index	= idx,				\
-		.fifo_size	= maxpkt,		\
-		.nr_banks	= maxbk,		\
-		.can_dma	= dma,			\
-		.can_isoc	= isoc,			\
-	}
-
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
-	defined(CONFIG_AT91SAM9X5)
-static struct usba_ep_data usba_udc_ep[] = {
-	EP("ep0", 0, 64, 1, 0, 0),
-	EP("ep1", 1, 1024, 2, 1, 1),
-	EP("ep2", 2, 1024, 2, 1, 1),
-	EP("ep3", 3, 1024, 3, 1, 0),
-	EP("ep4", 4, 1024, 3, 1, 0),
-	EP("ep5", 5, 1024, 3, 1, 1),
-	EP("ep6", 6, 1024, 3, 1, 1),
-};
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-static struct usba_ep_data usba_udc_ep[] = {
-	EP("ep0", 0, 64, 1, 0, 0),
-	EP("ep1", 1, 1024, 3, 1, 0),
-	EP("ep2", 2, 1024, 3, 1, 0),
-	EP("ep3", 3, 1024, 2, 1, 0),
-	EP("ep4", 4, 1024, 2, 1, 0),
-	EP("ep5", 5, 1024, 2, 1, 0),
-	EP("ep6", 6, 1024, 2, 1, 0),
-	EP("ep7", 7, 1024, 2, 1, 0),
-	EP("ep8", 8, 1024, 2, 0, 0),
-	EP("ep9", 9, 1024, 2, 0, 0),
-	EP("ep10", 10, 1024, 2, 0, 0),
-	EP("ep11", 11, 1024, 2, 0, 0),
-	EP("ep12", 12, 1024, 2, 0, 0),
-	EP("ep13", 13, 1024, 2, 0, 0),
-	EP("ep14", 14, 1024, 2, 0, 0),
-	EP("ep15", 15, 1024, 2, 0, 0),
-};
-#else
-# error "NO usba_udc_ep defined"
-#endif
-
-#undef EP
-
-struct usba_platform_data pdata = {
-	.num_ep	= ARRAY_SIZE(usba_udc_ep),
-	.ep	= usba_udc_ep,
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
deleted file mode 100644
index 1d45e2dc11..0000000000
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARM_ARCH_CLK_H__
-#define __ASM_ARM_ARCH_CLK_H__
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/global_data.h>
-
-static inline unsigned long get_cpu_clk_rate(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.cpu_clk_rate_hz;
-}
-
-static inline unsigned long get_main_clk_rate(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.main_clk_rate_hz;
-}
-
-static inline unsigned long get_mck_clk_rate(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.mck_rate_hz;
-}
-
-static inline unsigned long get_plla_clk_rate(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.plla_rate_hz;
-}
-
-static inline unsigned long get_pllb_clk_rate(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.pllb_rate_hz;
-}
-
-static inline u32 get_pllb_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	return gd->arch.at91_pllb_usb_init;
-}
-
-#ifdef CPU_HAS_H32MXDIV
-static inline unsigned int get_h32mxdiv(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
-}
-#else
-static inline unsigned int get_h32mxdiv(void)
-{
-	return 0;
-}
-#endif
-
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
-{
-	return get_mck_clk_rate();
-}
-
-static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-static inline unsigned long get_mci_clk_rate(void)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-static inline unsigned long get_pit_clk_rate(void)
-{
-	if (get_h32mxdiv())
-		return get_mck_clk_rate() / 2;
-	else
-		return get_mck_clk_rate();
-}
-
-int at91_clock_init(unsigned long main_clock);
-void at91_periph_clk_enable(int id);
-void at91_periph_clk_disable(int id);
-#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
deleted file mode 100644
index 6d2a7b72ff..0000000000
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h]
- *
- *  Copyright (C) 2005 HP Labs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_AT91_GPIO_H
-#define __ASM_ARCH_AT91_GPIO_H
-
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_ATMEL_LEGACY
-
-#define PIN_BASE		0
-
-#define MAX_GPIO_BANKS		5
-
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-
-#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
-#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
-#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
-#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
-#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
-#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
-#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
-#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
-#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
-#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
-#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
-#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
-#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
-#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
-#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
-#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
-#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
-#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
-#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
-#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
-#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
-#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
-#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
-#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
-#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
-#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
-#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
-#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
-#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
-#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
-#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
-#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
-
-#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
-#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
-#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
-#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
-#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
-#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
-#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
-#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
-#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
-#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
-#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
-#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
-#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
-#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
-#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
-#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
-#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
-#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
-#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
-#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
-#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
-#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
-#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
-#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
-#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
-#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
-#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
-#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
-#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
-#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
-#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
-#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
-
-#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
-#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
-#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
-#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
-#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
-#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
-#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
-#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
-#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
-#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
-#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
-#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
-#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
-#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
-#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
-#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
-#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
-#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
-#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
-#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
-#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
-#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
-#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
-#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
-#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
-#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
-#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
-#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
-#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
-#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
-#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
-#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
-
-#define	AT91_PIN_PD0	(PIN_BASE + 0x60 + 0)
-#define	AT91_PIN_PD1	(PIN_BASE + 0x60 + 1)
-#define	AT91_PIN_PD2	(PIN_BASE + 0x60 + 2)
-#define	AT91_PIN_PD3	(PIN_BASE + 0x60 + 3)
-#define	AT91_PIN_PD4	(PIN_BASE + 0x60 + 4)
-#define	AT91_PIN_PD5	(PIN_BASE + 0x60 + 5)
-#define	AT91_PIN_PD6	(PIN_BASE + 0x60 + 6)
-#define	AT91_PIN_PD7	(PIN_BASE + 0x60 + 7)
-#define	AT91_PIN_PD8	(PIN_BASE + 0x60 + 8)
-#define	AT91_PIN_PD9	(PIN_BASE + 0x60 + 9)
-#define	AT91_PIN_PD10	(PIN_BASE + 0x60 + 10)
-#define	AT91_PIN_PD11	(PIN_BASE + 0x60 + 11)
-#define	AT91_PIN_PD12	(PIN_BASE + 0x60 + 12)
-#define	AT91_PIN_PD13	(PIN_BASE + 0x60 + 13)
-#define	AT91_PIN_PD14	(PIN_BASE + 0x60 + 14)
-#define	AT91_PIN_PD15	(PIN_BASE + 0x60 + 15)
-#define	AT91_PIN_PD16	(PIN_BASE + 0x60 + 16)
-#define	AT91_PIN_PD17	(PIN_BASE + 0x60 + 17)
-#define	AT91_PIN_PD18	(PIN_BASE + 0x60 + 18)
-#define	AT91_PIN_PD19	(PIN_BASE + 0x60 + 19)
-#define	AT91_PIN_PD20	(PIN_BASE + 0x60 + 20)
-#define	AT91_PIN_PD21	(PIN_BASE + 0x60 + 21)
-#define	AT91_PIN_PD22	(PIN_BASE + 0x60 + 22)
-#define	AT91_PIN_PD23	(PIN_BASE + 0x60 + 23)
-#define	AT91_PIN_PD24	(PIN_BASE + 0x60 + 24)
-#define	AT91_PIN_PD25	(PIN_BASE + 0x60 + 25)
-#define	AT91_PIN_PD26	(PIN_BASE + 0x60 + 26)
-#define	AT91_PIN_PD27	(PIN_BASE + 0x60 + 27)
-#define	AT91_PIN_PD28	(PIN_BASE + 0x60 + 28)
-#define	AT91_PIN_PD29	(PIN_BASE + 0x60 + 29)
-#define	AT91_PIN_PD30	(PIN_BASE + 0x60 + 30)
-#define	AT91_PIN_PD31	(PIN_BASE + 0x60 + 31)
-
-#define	AT91_PIN_PE0	(PIN_BASE + 0x80 + 0)
-#define	AT91_PIN_PE1	(PIN_BASE + 0x80 + 1)
-#define	AT91_PIN_PE2	(PIN_BASE + 0x80 + 2)
-#define	AT91_PIN_PE3	(PIN_BASE + 0x80 + 3)
-#define	AT91_PIN_PE4	(PIN_BASE + 0x80 + 4)
-#define	AT91_PIN_PE5	(PIN_BASE + 0x80 + 5)
-#define	AT91_PIN_PE6	(PIN_BASE + 0x80 + 6)
-#define	AT91_PIN_PE7	(PIN_BASE + 0x80 + 7)
-#define	AT91_PIN_PE8	(PIN_BASE + 0x80 + 8)
-#define	AT91_PIN_PE9	(PIN_BASE + 0x80 + 9)
-#define	AT91_PIN_PE10	(PIN_BASE + 0x80 + 10)
-#define	AT91_PIN_PE11	(PIN_BASE + 0x80 + 11)
-#define	AT91_PIN_PE12	(PIN_BASE + 0x80 + 12)
-#define	AT91_PIN_PE13	(PIN_BASE + 0x80 + 13)
-#define	AT91_PIN_PE14	(PIN_BASE + 0x80 + 14)
-#define	AT91_PIN_PE15	(PIN_BASE + 0x80 + 15)
-#define	AT91_PIN_PE16	(PIN_BASE + 0x80 + 16)
-#define	AT91_PIN_PE17	(PIN_BASE + 0x80 + 17)
-#define	AT91_PIN_PE18	(PIN_BASE + 0x80 + 18)
-#define	AT91_PIN_PE19	(PIN_BASE + 0x80 + 19)
-#define	AT91_PIN_PE20	(PIN_BASE + 0x80 + 20)
-#define	AT91_PIN_PE21	(PIN_BASE + 0x80 + 21)
-#define	AT91_PIN_PE22	(PIN_BASE + 0x80 + 22)
-#define	AT91_PIN_PE23	(PIN_BASE + 0x80 + 23)
-#define	AT91_PIN_PE24	(PIN_BASE + 0x80 + 24)
-#define	AT91_PIN_PE25	(PIN_BASE + 0x80 + 25)
-#define	AT91_PIN_PE26	(PIN_BASE + 0x80 + 26)
-#define	AT91_PIN_PE27	(PIN_BASE + 0x80 + 27)
-#define	AT91_PIN_PE28	(PIN_BASE + 0x80 + 28)
-#define	AT91_PIN_PE29	(PIN_BASE + 0x80 + 29)
-#define	AT91_PIN_PE30	(PIN_BASE + 0x80 + 30)
-#define	AT91_PIN_PE31	(PIN_BASE + 0x80 + 31)
-
-static unsigned long at91_pios[] = {
-	ATMEL_BASE_PIOA,
-	ATMEL_BASE_PIOB,
-	ATMEL_BASE_PIOC,
-#ifdef ATMEL_BASE_PIOD
-	ATMEL_BASE_PIOD,
-#ifdef ATMEL_BASE_PIOE
-	ATMEL_BASE_PIOE
-#endif
-#endif
-};
-
-static inline void *pin_to_controller(unsigned pin)
-{
-	pin -= PIN_BASE;
-	pin /= 32;
-	return (void *)(at91_pios[pin]);
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
-	pin -= PIN_BASE;
-	return 1 << (pin % 32);
-}
-
-/* The following macros are need for backward compatibility */
-#define at91_set_GPIO_periph(x, y) \
-	at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_A_periph(x, y) \
-	at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_B_periph(x, y) \
-	at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_output(x, y) \
-	at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_input(x, y) \
-	at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_set_gpio_value(x, y) \
-	at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y)
-#define at91_get_gpio_value(x) \
-	at91_get_pio_value((x - PIN_BASE) / 32,(x % 32))
-#else
-#define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
-#define at91_get_gpio_value(x)		at91_get_pio_value(x)
-#endif
-
-#define GPIO_PIOA_BASE  (0)
-#define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
-#define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
-#define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
-#define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PA(x)  (GPIO_PIOA_BASE + (x))
-#define GPIO_PIN_PB(x)  (GPIO_PIOB_BASE + (x))
-#define GPIO_PIN_PC(x)  (GPIO_PIOC_BASE + (x))
-#define GPIO_PIN_PD(x)  (GPIO_PIOD_BASE + (x))
-#define GPIO_PIN_PE(x)  (GPIO_PIOE_BASE + (x))
-
-static inline unsigned at91_gpio_to_port(unsigned gpio)
-{
-	return gpio / 32;
-}
-
-static inline unsigned at91_gpio_to_pin(unsigned gpio)
-{
-	return gpio % 32;
-}
-
-/* Platform data for each GPIO port */
-struct at91_port_platdata {
-	uint32_t base_addr;
-	const char *bank_name;
-};
-
-#endif /* __ASM_ARCH_AT91_GPIO_H */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
deleted file mode 100644
index ff6b71b135..0000000000
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARM_ARCH_HARDWARE_H__
-#define __ASM_ARM_ARCH_HARDWARE_H__
-
-#if defined(CONFIG_AT91RM9200)
-# include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \
-	defined(CONFIG_AT91SAM9XE)
-# include <asm/arch/at91sam9260.h>
-#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
-# include <asm/arch/at91sam9261.h>
-#elif defined(CONFIG_AT91SAM9263)
-# include <asm/arch/at91sam9263.h>
-#elif defined(CONFIG_AT91SAM9RL)
-# include <asm/arch/at91sam9rl.h>
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
-# include <asm/arch/at91sam9g45.h>
-#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
-# include <asm/arch/at91sam9x5.h>
-#elif defined(CONFIG_SAMA5D3)
-# include <asm/arch/sama5d3.h>
-#elif defined(CONFIG_SAMA5D4)
-# include <asm/arch/sama5d4.h>
-#else
-# error "Unsupported AT91 processor"
-#endif
-
-#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/include/asm/arch-at91/sama5_matrix.h b/arch/arm/include/asm/arch-at91/sama5_matrix.h
deleted file mode 100644
index e324766733..0000000000
--- a/arch/arm/include/asm/arch-at91/sama5_matrix.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Bus Matrix header file for the SAMA5 family
- *
- * Copyright (C) 2014 Atmel
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SAMA5_MATRIX_H
-#define __SAMA5_MATRIX_H
-
-struct atmel_matrix {
-	u32 mcfg[16];	/* 0x00 ~ 0x3c: Master Configuration Register */
-	u32 scfg[16];	/* 0x40 ~ 0x7c: Slave Configuration Register */
-	u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
-	u32 res1[20];	/* 0x100 ~ 0x14c */
-	u32 meier;	/* 0x150: Master Error Interrupt Enable Register */
-	u32 meidr;	/* 0x154: Master Error Interrupt Disable Register */
-	u32 meimr;	/* 0x158: Master Error Interrupt Mask Register */
-	u32 mesr;	/* 0x15c: Master Error Status Register */
-	u32 mear[16];	/* 0x160 ~ 0x19c: Master Error Address Register */
-	u32 res2[17];	/* 0x1A0 ~ 0x1E0 */
-	u32 wpmr;	/* 0x1E4: Write Protection Mode Register */
-	u32 wpsr;	/* 0x1E8: Write Protection Status Register */
-	u32 res3[5];	/* 0x1EC ~ 0x1FC */
-	u32 ssr[16];	/* 0x200 ~ 0x23c: Security Slave Register */
-	u32 sassr[16];	/* 0x240 ~ 0x27c: Security Areas Split Slave Register */
-	u32 srtsr[16];	/* 0x280 ~ 0x2bc: Security Region Top Slave */
-	u32 spselr[3];	/* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
-};
-
-/* Bit field in WPMR */
-#define ATMEL_MATRIX_WPMR_WPKEY	0x4D415400
-#define ATMEL_MATRIX_WPMR_WPEN	0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5_sfr.h b/arch/arm/include/asm/arch-at91/sama5_sfr.h
deleted file mode 100644
index 3081d37571..0000000000
--- a/arch/arm/include/asm/arch-at91/sama5_sfr.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Special Function Register (SFR)
- *
- * Copyright (C) 2014 Atmel
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
-
-struct atmel_sfr {
-	u32 reserved1;	/* 0x00 */
-	u32 ddrcfg;	/* 0x04: DDR Configuration Register */
-	u32 reserved2;	/* 0x08 */
-	u32 reserved3;	/* 0x0c */
-	u32 ohciicr;	/* 0x10: OHCI Interrupt Configuration Register */
-	u32 ohciisr;	/* 0x14: OHCI Interrupt Status Register */
-	u32 reserved4[4];	/* 0x18 ~ 0x24 */
-	u32 secure;		/* 0x28: Security Configuration Register */
-	u32 reserved5[5];	/* 0x2c ~ 0x3c */
-	u32 ebicfg;		/* 0x40: EBI Configuration Register */
-	u32 reserved6[2];	/* 0x44 ~ 0x48 */
-	u32 sn0;		/* 0x4c */
-	u32 sn1;		/* 0x50 */
-	u32 aicredir;	/* 0x54 */
-};
-
-/* Bit field in DDRCFG */
-#define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
-#define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
-
-/* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_KEY		0x5F67B102
-#define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
deleted file mode 100644
index 227ba80825..0000000000
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D3 family
- *
- * (C) 2012 - 2013 Atmel Corporation.
- * Bo Shen <voice.shen@atmel.com>
- *
- * Definitions for the SoC:
- * SAMA5D3
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef SAMA5D3_H
-#define SAMA5D3_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* it's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
-#define ATMEL_ID_SYS	1	/* System Controller Interrupt */
-#define ATMEL_ID_DBGU	2	/* Debug Unit Interrupt */
-#define ATMEL_ID_PIT	3	/* Periodic Interval Timer Interrupt */
-#define ATMEL_ID_WDT	4	/* Watchdog timer Interrupt */
-#define ATMEL_ID_SMC	5	/* Multi-bit ECC Interrupt */
-#define ATMEL_ID_PIOA	6	/* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB	7	/* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC	8	/* Parallel I/O Controller C */
-#define ATMEL_ID_PIOD	9	/* Parallel I/O Controller D */
-#define ATMEL_ID_PIOE	10	/* Parallel I/O Controller E */
-#define ATMEL_ID_SMD	11	/* SMD Soft Modem */
-#define ATMEL_ID_USART0	12	/* USART 0 */
-#define ATMEL_ID_USART1	13	/* USART 1 */
-#define ATMEL_ID_USART2	14	/* USART 2 */
-#define ATMEL_ID_USART3	15	/* USART 3 */
-#define ATMEL_ID_UART0	16
-#define ATMEL_ID_UART1	17
-#define ATMEL_ID_TWI0	18	/* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1	19	/* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2	20	/* Two-Wire Interface 2 */
-#define ATMEL_ID_MCI0	21	/* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1	22	/*  */
-#define ATMEL_ID_MCI2	23	/*  */
-#define ATMEL_ID_SPI0	24	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	25	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_TC0	26	/* */
-#define ATMEL_ID_TC1	27	/* */
-#define ATMEL_ID_PWMC	28	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_TSC	29	/* Touch Screen ADC Controller */
-#define ATMEL_ID_DMA0	30	/* DMA Controller */
-#define ATMEL_ID_DMA1	31	/* DMA Controller */
-#define ATMEL_ID_UHPHS	32	/* USB Host High Speed */
-#define ATMEL_ID_UDPHS	33	/* USB Device High Speed */
-#define ATMEL_ID_GMAC	34
-#define ATMEL_ID_EMAC	35	/* Ethernet MAC */
-#define ATMEL_ID_LCDC	36	/* LCD Controller */
-#define ATMEL_ID_ISI	37	/* Image Sensor Interface */
-#define ATMEL_ID_SSC0	38	/* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1	39	/* Synchronous Serial Controller 1 */
-#define ATMEL_ID_CAN0	40
-#define ATMEL_ID_CAN1	41
-#define ATMEL_ID_SHA	42
-#define ATMEL_ID_AES	43
-#define ATMEL_ID_TDES	44
-#define ATMEL_ID_TRNG	45
-#define ATMEL_ID_ARM	46
-#define ATMEL_ID_IRQ0	47	/* Advanced Interrupt Controller */
-#define ATMEL_ID_FUSE	48
-#define ATMEL_ID_MPDDRC	49
-
-/* sama5d3 series chip id definitions */
-#define ARCH_ID_SAMA5D3		0x8a5c07c0
-#define ARCH_EXID_SAMA5D31	0x00444300
-#define ARCH_EXID_SAMA5D33	0x00414300
-#define ARCH_EXID_SAMA5D34	0x00414301
-#define ARCH_EXID_SAMA5D35	0x00584300
-#define ARCH_EXID_SAMA5D36	0x00004301
-
-#define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
-#define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D31))
-#define cpu_is_sama5d33()	(cpu_is_sama5d3() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D33))
-#define cpu_is_sama5d34()	(cpu_is_sama5d3() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
-#define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
-#define cpu_is_sama5d36()	(cpu_is_sama5d3() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_MCI0		0xf0000000
-#define ATMEL_BASE_SPI0		0xf0004000
-#define ATMEL_BASE_SSC0		0xf000C000
-#define ATMEL_BASE_TC2		0xf0010000
-#define ATMEL_BASE_TWI0		0xf0014000
-#define ATMEL_BASE_TWI1		0xf0018000
-#define ATMEL_BASE_USART0	0xf001c000
-#define ATMEL_BASE_USART1	0xf0020000
-#define ATMEL_BASE_UART0	0xf0024000
-#define ATMEL_BASE_GMAC		0xf0028000
-#define ATMEL_BASE_PWMC		0xf002c000
-#define ATMEL_BASE_LCDC		0xf0030000
-#define ATMEL_BASE_ISI		0xf0034000
-#define ATMEL_BASE_SFR		0xf0038000
-/* Reserved: 0xf003c000 - 0xf8000000 */
-#define ATMEL_BASE_MCI1		0xf8000000
-#define ATMEL_BASE_MCI2		0xf8004000
-#define ATMEL_BASE_SPI1		0xf8008000
-#define ATMEL_BASE_SSC1		0xf800c000
-#define ATMEL_BASE_CAN1		0xf8010000
-#define ATMEL_BASE_TC3		0xf8014000
-#define ATMEL_BASE_TSADC	0xf8018000
-#define ATMEL_BASE_TWI2		0xf801c000
-#define ATMEL_BASE_USART2	0xf8020000
-#define ATMEL_BASE_USART3	0xf8024000
-#define ATMEL_BASE_UART1	0xf8028000
-#define ATMEL_BASE_EMAC		0xf802c000
-#define ATMEL_BASE_UDPHS	0xf8030000
-#define ATMEL_BASE_SHA		0xf8034000
-#define ATMEL_BASE_AES		0xf8038000
-#define ATMEL_BASE_TDES		0xf803c000
-#define ATMEL_BASE_TRNG		0xf8040000
-/* Reserved:	0xf804400 - 0xffffc00 */
-
-/*
- * System Peripherals physical base addresses.
- */
-#define ATMEL_BASE_SYS		0xffffc000
-#define ATMEL_BASE_SMC		0xffffc000
-#define ATMEL_BASE_PMECC	(ATMEL_BASE_SMC + 0x070)
-#define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_SMC + 0x500)
-#define ATMEL_BASE_FUSE		0xffffe400
-#define ATMEL_BASE_DMAC0	0xffffe600
-#define ATMEL_BASE_DMAC1	0xffffe800
-#define ATMEL_BASE_MPDDRC	0xffffea00
-#define ATMEL_BASE_MATRIX	0xffffec00
-#define ATMEL_BASE_DBGU		0xffffee00
-#define ATMEL_BASE_AIC		0xfffff000
-#define ATMEL_BASE_PIOA		0xfffff200
-#define ATMEL_BASE_PIOB		0xfffff400
-#define ATMEL_BASE_PIOC		0xfffff600
-#define ATMEL_BASE_PIOD		0xfffff800
-#define ATMEL_BASE_PIOE		0xfffffa00
-#define ATMEL_BASE_PMC		0xfffffc00
-#define ATMEL_BASE_RSTC		0xfffffe00
-#define ATMEL_BASE_SHDWN	0xfffffe10
-#define ATMEL_BASE_PIT		0xfffffe30
-#define ATMEL_BASE_WDT		0xfffffe40
-#define ATMEL_BASE_SCKCR	0xfffffe50
-#define ATMEL_BASE_GPBR		0xfffffe60
-#define ATMEL_BASE_RTC		0xfffffeb0
-/* Reserved:	0xfffffee0 - 0xffffffff */
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM		0x00100000	/* Internal ROM base address */
-#define ATMEL_BASE_SRAM		0x00200000	/* Internal ROM base address */
-#define ATMEL_BASE_SRAM0	0x00300000	/* Internal SRAM base address */
-#define ATMEL_BASE_SRAM1	0x00310000	/* Internal SRAM base address */
-#define ATMEL_BASE_SMD		0x00400000	/* Internal ROM base address */
-#define ATMEL_BASE_UDPHS_FIFO	0x00500000	/* USB Device HS controller */
-#define ATMEL_BASE_OHCI		0x00600000	/* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI		0x00700000	/* USB Host controller (EHCI) */
-#define ATMEL_BASE_AXI		0x00800000	/* Video Decoder Controller */
-#define ATMEL_BASE_DAP		0x00900000	/* Video Decoder Controller */
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000
-#define ATMEL_BASE_DDRCS	0x20000000
-#define ATMEL_BASE_CS1		0x40000000
-#define ATMEL_BASE_CS2		0x50000000
-#define ATMEL_BASE_CS3		0x60000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV		0x3fff
-#define CPU_HAS_PCR
-
-/*
- * PMECC table in ROM
- */
-#define ATMEL_PMECC_INDEX_OFFSET_512	0x10000
-#define ATMEL_PMECC_INDEX_OFFSET_1024	0x18000
-
-/*
- * SAMA5D3 specific prototypes
- */
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_emac(void);
-unsigned int has_gmac(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
deleted file mode 100644
index a859b6db9b..0000000000
--- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2012 Atmel Corporation.
- *
- * Static Memory Controllers (SMC) - System peripherals registers.
- * Based on SAMA5D3 datasheet.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef SAMA5D3_SMC_H
-#define SAMA5D3_SMC_H
-
-#ifdef __ASSEMBLY__
-#define AT91_ASM_SMC_SETUP0	(ATMEL_BASE_SMC + 0x600)
-#define AT91_ASM_SMC_PULSE0	(ATMEL_BASE_SMC + 0x604)
-#define AT91_ASM_SMC_CYCLE0	(ATMEL_BASE_SMC + 0x608)
-#define AT91_ASM_SMC_TIMINGS0	(ATMEL_BASE_SMC + 0x60c)
-#define AT91_ASM_SMC_MODE0	(ATMEL_BASE_SMC + 0x610)
-#else
-struct at91_cs {
-	u32	setup;		/* 0x600 SMC Setup Register */
-	u32	pulse;		/* 0x604 SMC Pulse Register */
-	u32	cycle;		/* 0x608 SMC Cycle Register */
-	u32	timings;	/* 0x60C SMC Cycle Register */
-	u32	mode;		/* 0x610 SMC Mode Register */
-};
-
-struct at91_smc {
-	u32 reserved[384];
-	struct at91_cs cs[4];
-};
-#endif /*  __ASSEMBLY__ */
-
-#define AT91_SMC_SETUP_NWE(x)		(x & 0x3f)
-#define AT91_SMC_SETUP_NCS_WR(x)	((x & 0x3f) << 8)
-#define AT91_SMC_SETUP_NRD(x)		((x & 0x3f) << 16)
-#define AT91_SMC_SETUP_NCS_RD(x)	((x & 0x3f) << 24)
-
-#define AT91_SMC_PULSE_NWE(x)		(x & 0x3f)
-#define AT91_SMC_PULSE_NCS_WR(x)	((x & 0x3f) << 8)
-#define AT91_SMC_PULSE_NRD(x)		((x & 0x3f) << 16)
-#define AT91_SMC_PULSE_NCS_RD(x)	((x & 0x3f) << 24)
-
-#define AT91_SMC_CYCLE_NWE(x)		(x & 0x1ff)
-#define AT91_SMC_CYCLE_NRD(x)		((x & 0x1ff) << 16)
-
-#define AT91_SMC_TIMINGS_TCLR(x)	(x & 0xf)
-#define AT91_SMC_TIMINGS_TADL(x)	((x & 0xf) << 4)
-#define AT91_SMC_TIMINGS_TAR(x)		((x & 0xf) << 8)
-#define AT91_SMC_TIMINGS_OCMS(x)	((x & 0x1) << 12)
-#define AT91_SMC_TIMINGS_TRR(x)		((x & 0xf) << 16)
-#define AT91_SMC_TIMINGS_TWB(x)		((x & 0xf) << 24)
-#define AT91_SMC_TIMINGS_RBNSEL(x)	((x & 0xf) << 28)
-#define AT91_SMC_TIMINGS_NFSEL(x)	((x & 0x1) << 31)
-
-#define AT91_SMC_MODE_RM_NCS		0x00000000
-#define AT91_SMC_MODE_RM_NRD		0x00000001
-#define AT91_SMC_MODE_WM_NCS		0x00000000
-#define AT91_SMC_MODE_WM_NWE		0x00000002
-
-#define AT91_SMC_MODE_EXNW_DISABLE	0x00000000
-#define AT91_SMC_MODE_EXNW_FROZEN	0x00000020
-#define AT91_SMC_MODE_EXNW_READY	0x00000030
-
-#define AT91_SMC_MODE_BAT		0x00000100
-#define AT91_SMC_MODE_DBW_8		0x00000000
-#define AT91_SMC_MODE_DBW_16		0x00001000
-#define AT91_SMC_MODE_DBW_32		0x00002000
-#define AT91_SMC_MODE_TDF_CYCLE(x)	((x & 0xf) << 16)
-#define AT91_SMC_MODE_TDF		0x00100000
-#define AT91_SMC_MODE_PMEN		0x01000000
-#define AT91_SMC_MODE_PS_4		0x00000000
-#define AT91_SMC_MODE_PS_8		0x10000000
-#define AT91_SMC_MODE_PS_16		0x20000000
-#define AT91_SMC_MODE_PS_32		0x30000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/include/asm/arch-at91/sama5d4.h
deleted file mode 100644
index f30cb5fed1..0000000000
--- a/arch/arm/include/asm/arch-at91/sama5d4.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D4 SoC
- *
- * Copyright (C) 2014 Atmel
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __SAMA5D4_H
-#define __SAMA5D4_H
-
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* It's a member of AT91 */
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define ATMEL_ID_FIQ	0	/* FIQ Interrupt */
-#define ATMEL_ID_SYS	1	/* System Controller */
-#define ATMEL_ID_ARM	2	/* Performance Monitor Unit */
-#define ATMEL_ID_PIT	3	/* Periodic Interval Timer */
-#define ATMEL_ID_WDT	4	/* Watchdog timer */
-#define ATMEL_ID_PIOD	5	/* Parallel I/O Controller D */
-#define ATMEL_ID_USART0	6	/* USART 0 */
-#define ATMEL_ID_USART1	7	/* USART 1 */
-#define ATMEL_ID_DMA0	8	/* DMA Controller 0 */
-#define ATMEL_ID_ICM	9	/* Integrity Check Monitor */
-#define ATMEL_ID_PKCC	10	/* Public Key Crypto Controller */
-#define ATMEL_ID_AES	12	/* Advanced Encryption Standard */
-#define ATMEL_ID_AESB	13	/* AES Bridge*/
-#define ATMEL_ID_TDES	14	/* Triple Data Encryption Standard */
-#define ATMEL_ID_SHA    15	/* SHA Signature */
-#define ATMEL_ID_MPDDRC	16	/* MPDDR controller */
-#define ATMEL_ID_MATRIX1	17	/* H32MX, 32-bit AHB Matrix */
-#define ATMEL_ID_MATRIX0	18	/* H64MX, 64-bit AHB Matrix */
-#define ATMEL_ID_VDEC	19	/* Video Decoder */
-#define ATMEL_ID_SBM	20	/* Secure Box Module */
-#define ATMEL_ID_SMC	22	/* Multi-bit ECC interrupt */
-#define ATMEL_ID_PIOA	23	/* Parallel I/O Controller A */
-#define ATMEL_ID_PIOB	24	/* Parallel I/O Controller B */
-#define ATMEL_ID_PIOC	25	/* Parallel I/O Controller C */
-#define ATMEL_ID_PIOE	26	/* Parallel I/O Controller E */
-#define ATMEL_ID_UART0	27	/* UART 0 */
-#define ATMEL_ID_UART1	28	/* UART 1 */
-#define ATMEL_ID_USART2	29	/* USART 2 */
-#define ATMEL_ID_USART3	30	/* USART 3 */
-#define ATMEL_ID_USART4	31	/* USART 4 */
-#define ATMEL_ID_TWI0	32	/* Two-Wire Interface 0 */
-#define ATMEL_ID_TWI1	33	/* Two-Wire Interface 1 */
-#define ATMEL_ID_TWI2	34	/* Two-Wire Interface 2 */
-#define ATMEL_ID_MCI0	35	/* High Speed Multimedia Card Interface 0 */
-#define ATMEL_ID_MCI1	36	/* High Speed Multimedia Card Interface 1 */
-#define ATMEL_ID_SPI0	37	/* Serial Peripheral Interface 0 */
-#define ATMEL_ID_SPI1	38	/* Serial Peripheral Interface 1 */
-#define ATMEL_ID_SPI2	39	/* Serial Peripheral Interface 2 */
-#define ATMEL_ID_TC0	40	/* Timer Counter 0 (ch. 0, 1, 2) */
-#define ATMEL_ID_TC1	41	/* Timer Counter 1 (ch. 3, 4, 5) */
-#define ATMEL_ID_TC2	42	/* Timer Counter 2 (ch. 6, 7, 8) */
-#define ATMEL_ID_PWMC	43	/* Pulse Width Modulation Controller */
-#define ATMEL_ID_ADC	44	/* Touch Screen ADC Controller */
-#define ATMEL_ID_DBGU	45	/* Debug Unit Interrupt */
-#define ATMEL_ID_UHPHS	46	/* USB Host High Speed */
-#define ATMEL_ID_UDPHS	47	/* USB Device High Speed */
-#define ATMEL_ID_SSC0	48	/* Synchronous Serial Controller 0 */
-#define ATMEL_ID_SSC1	49	/* Synchronous Serial Controller 1 */
-#define ATMEL_ID_XDMAC1	50	/* DMA Controller 1 */
-#define ATMEL_ID_LCDC	51	/* LCD Controller */
-#define ATMEL_ID_ISI	52	/* Image Sensor Interface */
-#define ATMEL_ID_TRNG	53	/* True Random Number Generator */
-#define ATMEL_ID_GMAC0	54	/* Ethernet MAC 0 */
-#define ATMEL_ID_GMAC1	55	/* Ethernet MAC 1 */
-#define ATMEL_ID_IRQ	56	/* IRQ Interrupt ID */
-#define ATMEL_ID_SFC	57	/* Fuse Controller */
-#define ATMEL_ID_SECURAM	59	/* Secured RAM */
-#define ATMEL_ID_SMD	61	/* SMD Soft Modem */
-#define ATMEL_ID_TWI3	62	/* Two-Wire Interface 3 */
-#define ATMEL_ID_CATB	63	/* Capacitive Touch Controller */
-#define ATMEL_ID_SFR	64	/* Special Funcion Register */
-#define ATMEL_ID_AIC	65	/* Advanced Interrupt Controller */
-#define ATMEL_ID_SAIC	66	/* Secured Advanced Interrupt Controller */
-#define ATMEL_ID_L2CC	67	/* L2 Cache Controller */
-
-/*
- * User Peripherals physical base addresses.
- */
-#define ATMEL_BASE_LCDC		0xf0000000
-#define ATMEL_BASE_DMAC1	0xf0004000
-#define ATMEL_BASE_ISI		0xf0008000
-#define ATMEL_BASE_PKCC		0xf000C000
-#define ATMEL_BASE_MPDDRC	0xf0010000
-#define ATMEL_BASE_DMAC0	0xf0014000
-#define ATMEL_BASE_PMC		0xf0018000
-#define ATMEL_BASE_MATRIX0	0xf001c000
-#define ATMEL_BASE_AESB		0xf0020000
-/* Reserved: 0xf0024000 - 0xf8000000 */
-#define ATMEL_BASE_MCI0		0xf8000000
-#define ATMEL_BASE_UART0	0xf8004000
-#define ATMEL_BASE_SSC0		0xf8008000
-#define ATMEL_BASE_PWMC		0xf800c000
-#define ATMEL_BASE_SPI0		0xf8010000
-#define ATMEL_BASE_TWI0		0xf8014000
-#define ATMEL_BASE_TWI1		0xf8018000
-#define ATMEL_BASE_TC0		0xf801c000
-#define ATMEL_BASE_GMAC0	0xf8020000
-#define ATMEL_BASE_TWI2		0xf8024000
-#define ATMEL_BASE_SFR		0xf8028000
-#define ATMEL_BASE_USART0	0xf802c000
-#define ATMEL_BASE_USART1	0xf8030000
-/* Reserved:	0xf8034000 - 0xfc000000 */
-#define ATMEL_BASE_MCI1		0xfc000000
-#define ATMEL_BASE_UART1	0xfc004000
-#define ATMEL_BASE_USART2	0xfc008000
-#define ATMEL_BASE_USART3	0xfc00c000
-#define ATMEL_BASE_USART4	0xfc010000
-#define ATMEL_BASE_SSC1		0xfc014000
-#define ATMEL_BASE_SPI1		0xfc018000
-#define ATMEL_BASE_SPI2		0xfc01c000
-#define ATMEL_BASE_TC1		0xfc020000
-#define ATMEL_BASE_TC2		0xfc024000
-#define ATMEL_BASE_GMAC1	0xfc028000
-#define ATMEL_BASE_UDPHS	0xfc02c000
-#define ATMEL_BASE_TRNG		0xfc030000
-#define ATMEL_BASE_ADC		0xfc034000
-#define ATMEL_BASE_TWI3		0xfc038000
-
-#define ATMEL_BASE_MATRIX1	0xfc054000
-
-#define ATMEL_BASE_SMC		0xfc05c000
-#define ATMEL_BASE_PMECC	(ATMEL_BASE_SMC + 0x070)
-#define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_SMC + 0x500)
-
-#define ATMEL_BASE_PIOD		0xfc068000
-#define ATMEL_BASE_RSTC		0xfc068600
-#define ATMEL_BASE_PIT		0xfc068630
-#define ATMEL_BASE_WDT		0xfc068640
-
-#define ATMEL_BASE_DBGU		0xfc069000
-#define ATMEL_BASE_PIOA		0xfc06a000
-#define ATMEL_BASE_PIOB		0xfc06b000
-#define ATMEL_BASE_PIOC		0xfc06c000
-#define ATMEL_BASE_PIOE		0xfc06d000
-#define ATMEL_BASE_AIC		0xfc06e000
-
-/*
- * Internal Memory.
- */
-#define ATMEL_BASE_ROM		0x00000000	/* Internal ROM base address */
-#define ATMEL_BASE_NFC		0x00100000	/* NFC SRAM */
-#define ATMEL_BASE_SRAM		0x00200000	/* Internal ROM base address */
-#define ATMEL_BASE_VDEC		0x00300000	/* Video Decoder Controller */
-#define ATMEL_BASE_UDPHS_FIFO	0x00400000	/* USB Device HS controller */
-#define ATMEL_BASE_OHCI		0x00500000	/* USB Host controller (OHCI) */
-#define ATMEL_BASE_EHCI		0x00600000	/* USB Host controller (EHCI) */
-#define ATMEL_BASE_AXI		0x00700000
-#define ATMEL_BASE_DAP		0x00800000
-#define ATMEL_BASE_SMD		0x00900000
-
-/*
- * External memory
- */
-#define ATMEL_BASE_CS0		0x10000000
-#define ATMEL_BASE_DDRCS	0x20000000
-#define ATMEL_BASE_CS1		0x60000000
-#define ATMEL_BASE_CS2		0x70000000
-#define ATMEL_BASE_CS3		0x80000000
-
-/*
- * Other misc defines
- */
-#define ATMEL_PIO_PORTS		5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV		0x3fff
-#define CPU_HAS_PCR
-#define CPU_HAS_H32MXDIV
-
-/* sama5d4 series chip id definitions */
-#define ARCH_ID_SAMA5D4		0x8a5c07c0
-#define ARCH_EXID_SAMA5D41	0x00000001
-#define ARCH_EXID_SAMA5D42	0x00000002
-#define ARCH_EXID_SAMA5D43	0x00000003
-#define ARCH_EXID_SAMA5D44	0x00000004
-
-#define cpu_is_sama5d4()	(get_chip_id() == ARCH_ID_SAMA5D4)
-#define cpu_is_sama5d41()	(cpu_is_sama5d4() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D41))
-#define cpu_is_sama5d42()	(cpu_is_sama5d4() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D42))
-#define cpu_is_sama5d43()	(cpu_is_sama5d4() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D43))
-#define cpu_is_sama5d44()	(cpu_is_sama5d4() && \
-		(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
-
-/*
- * No PMECC Galois table in ROM
- */
-#define NO_GALOIS_TABLE_IN_ROM
-
-#ifndef __ASSEMBLY__
-unsigned int get_chip_id(void);
-unsigned int get_extension_chip_id(void);
-unsigned int has_lcdc(void);
-char *get_cpu_name(void);
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h
index db42896201..c8ef8f528a 100644
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ b/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2012 Vikram Narayananan
  * <vikram186@gmail.com>
+ * (C) Copyright 2012,2015 Stephen Warren
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,7 +9,11 @@
 #ifndef _BCM2835_GPIO_H_
 #define _BCM2835_GPIO_H_
 
+#ifdef CONFIG_BCM2836
+#define BCM2835_GPIO_BASE		0x3f200000
+#else
 #define BCM2835_GPIO_BASE		0x20200000
+#endif
 #define BCM2835_GPIO_COUNT		54
 
 #define BCM2835_GPIO_FSEL_MASK		0x7
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 88d2ec11a7..04bf480a54 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -38,7 +38,11 @@
 
 /* Raw mailbox HW */
 
+#ifdef CONFIG_BCM2836
+#define BCM2835_MBOX_PHYSADDR	0x3f00b880
+#else
 #define BCM2835_MBOX_PHYSADDR	0x2000b880
+#endif
 
 struct bcm2835_mbox_regs {
 	u32 read;
@@ -121,6 +125,9 @@ struct bcm2835_mbox_tag_hdr {
 
 #define BCM2835_MBOX_TAG_GET_BOARD_REV	0x00010002
 
+#ifdef CONFIG_BCM2836
+#define BCM2836_BOARD_REV_2_B		0x4
+#else
 /*
  * 0x2..0xf from:
  * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
@@ -141,6 +148,7 @@ struct bcm2835_mbox_tag_hdr {
 #define BCM2835_BOARD_REV_B_PLUS	0x10
 #define BCM2835_BOARD_REV_CM		0x11
 #define BCM2835_BOARD_REV_A_PLUS	0x12
+#endif
 
 struct bcm2835_mbox_tag_get_board_rev {
 	struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h
index a4f867b2e9..2a21ccbf66 100644
--- a/arch/arm/include/asm/arch-bcm2835/sdhci.h
+++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h
@@ -1,23 +1,17 @@
 /*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _BCM2835_SDHCI_H_
 #define _BCM2835_SDHCI_H_
 
+#ifdef CONFIG_BCM2836
+#define BCM2835_SDHCI_BASE 0x3f300000
+#else
 #define BCM2835_SDHCI_BASE 0x20300000
+#endif
 
 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
 
diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h
index c2001b6f93..fc7aec7b7c 100644
--- a/arch/arm/include/asm/arch-bcm2835/timer.h
+++ b/arch/arm/include/asm/arch-bcm2835/timer.h
@@ -1,23 +1,17 @@
 /*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _BCM2835_TIMER_H
 #define _BCM2835_TIMER_H
 
+#ifdef CONFIG_BCM2836
+#define BCM2835_TIMER_PHYSADDR	0x3f003000
+#else
 #define BCM2835_TIMER_PHYSADDR	0x20003000
+#endif
 
 struct bcm2835_timer_regs {
 	u32 cs;
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h
index 303a65f32e..beb6a08206 100644
--- a/arch/arm/include/asm/arch-bcm2835/wdog.h
+++ b/arch/arm/include/asm/arch-bcm2835/wdog.h
@@ -1,23 +1,17 @@
 /*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _BCM2835_TIMER_H
 #define _BCM2835_TIMER_H
 
+#ifdef CONFIG_BCM2836
+#define BCM2835_WDOG_PHYSADDR			0x3f100000
+#else
 #define BCM2835_WDOG_PHYSADDR			0x20100000
+#endif
 
 struct bcm2835_wdog_regs {
 	u32 unknown0[7];
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h
deleted file mode 100644
index 5063e3964c..0000000000
--- a/arch/arm/include/asm/arch-davinci/aintc_defs.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_AINTC_DEFS_H_
-#define _DV_AINTC_DEFS_H_
-
-struct dv_aintc_regs {
-	unsigned int	fiq0;		/* 0x00 */
-	unsigned int	fiq1;		/* 0x04 */
-	unsigned int	irq0;		/* 0x08 */
-	unsigned int	irq1;		/* 0x0c */
-	unsigned int	fiqentry;	/* 0x10 */
-	unsigned int	irqentry;	/* 0x14 */
-	unsigned int	eint0;		/* 0x18 */
-	unsigned int	eint1;		/* 0x1c */
-	unsigned int	intctl;		/* 0x20 */
-	unsigned int	eabase;		/* 0x24 */
-	unsigned char	rsvd0[8];	/* 0x28 */
-	unsigned int	intpri0;	/* 0x30 */
-	unsigned int	intpri1;	/* 0x34 */
-	unsigned int	intpri2;	/* 0x38 */
-	unsigned int	intpri3;	/* 0x3c */
-	unsigned int	intpri4;	/* 0x40 */
-	unsigned int	intpri5;	/* 0x44 */
-	unsigned int	intpri6;	/* 0x48 */
-	unsigned int	intpri7;	/* 0x4c */
-};
-
-#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
-
-#define DV_AINTC_INTCTL_IDMODE	(1 << 2)
-
-#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
deleted file mode 100644
index 45a325c123..0000000000
--- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * SoC-specific lowlevel code for DA850
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __DA850_LOWLEVEL_H
-#define __DA850_LOWLEVEL_H
-
-#include <asm/arch/pinmux_defs.h>
-
-/* pinmux_resource[] vector is defined in the board specific file */
-extern const struct pinmux_resource pinmuxes[];
-extern const int pinmuxes_size;
-
-extern const struct lpsc_resource lpsc[];
-extern const int lpsc_size;
-
-/* NOR Boot Configuration Word Field Descriptions */
-#define DA850_NORBOOT_COPY_XK(X)	((X - 1) << 8)
-#define DA850_NORBOOT_METHOD_DIRECT	(1 << 4)
-#define DA850_NORBOOT_16BIT		(1 << 0)
-
-#define dv_maskbits(addr, val) \
-	writel((readl(addr) & val), addr)
-
-void da850_lpc_transition(unsigned char pscnum, unsigned char module,
-		unsigned char domain, unsigned char state);
-void da850_psc_init(void);
-void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
-	unsigned long value);
-
-#endif /* #ifndef __DA850_LOWLEVEL_H */
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-usb.h b/arch/arm/include/asm/arch-davinci/da8xx-usb.h
deleted file mode 100644
index f091e49899..0000000000
--- a/arch/arm/include/asm/arch-davinci/da8xx-usb.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
- *
- * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
- *
- * Based on drivers/usb/musb/davinci.h
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __DA8XX_MUSB_H__
-#define __DA8XX_MUSB_H__
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-/* Base address of da8xx usb0 wrapper */
-#define DA8XX_USB_OTG_BASE  0x01E00000
-
-/* Base address of da8xx musb core */
-#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
-
-/* Timeout for DA8xx usb module */
-#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
-
-/*
- * DA8xx platform USB wrapper register overlay.
- */
-struct da8xx_usb_regs {
-	dv_reg	revision;
-	dv_reg	control;
-	dv_reg 	status;
-	dv_reg 	emulation;
-	dv_reg 	mode;
-	dv_reg 	autoreq;
-	dv_reg 	srpfixtime;
-	dv_reg 	teardown;
-	dv_reg 	intsrc;
-	dv_reg 	intsrc_set;
-	dv_reg 	intsrc_clr;
-	dv_reg 	intmsk;
-	dv_reg 	intmsk_set;
-	dv_reg 	intmsk_clr;
-	dv_reg 	intsrcmsk;
-	dv_reg 	eoi;
-	dv_reg 	intvector;
-	dv_reg 	grndis_size[4];
-};
-
-#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
-
-/* DA8XX interrupt bits definitions */
-#define DA8XX_USB_TX_ENDPTS_MASK  0x1f	/* ep0 + 4 tx */
-#define DA8XX_USB_RX_ENDPTS_MASK  0x1e	/* 4 rx */
-#define DA8XX_USB_TXINT_SHIFT	  0
-#define DA8XX_USB_RXINT_SHIFT	  8
-
-#define DA8XX_USB_USBINT_MASK	  0x01ff0000	/* 8 Mentor, DRVVBUS */
-#define DA8XX_USB_TXINT_MASK \
-		(DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
-#define DA8XX_USB_RXINT_MASK \
-		(DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
-
-/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
-#define CFGCHIP2_PHYCLKGD	(1 << 17)
-#define CFGCHIP2_VBUSSENSE	(1 << 16)
-#define CFGCHIP2_RESET		(1 << 15)
-#define CFGCHIP2_OTGMODE	(3 << 13)
-#define CFGCHIP2_NO_OVERRIDE	(0 << 13)
-#define CFGCHIP2_FORCE_HOST	(1 << 13)
-#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
-#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
-#define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
-#define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
-#define CFGCHIP2_PHYPWRDN	(1 << 10)
-#define CFGCHIP2_OTGPWRDN	(1 << 9)
-#define CFGCHIP2_DATPOL 	(1 << 8)
-#define CFGCHIP2_USB1SUSPENDM	(1 << 7)
-#define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
-#define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */
-#define CFGCHIP2_VBDTCTEN	(1 << 4)	/* Vbus comparator */
-#define CFGCHIP2_REFFREQ	(0xf << 0)
-#define CFGCHIP2_REFFREQ_12MHZ	(1 << 0)
-#define CFGCHIP2_REFFREQ_24MHZ	(2 << 0)
-#define CFGCHIP2_REFFREQ_48MHZ	(3 << 0)
-
-#define DA8XX_USB_VBUS_GPIO	(1 << 15)
-
-int usb_phy_on(void);
-void usb_phy_off(void);
-
-#endif	/* __DA8XX_MUSB_H__ */
diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h
deleted file mode 100644
index 03be3882f8..0000000000
--- a/arch/arm/include/asm/arch-davinci/davinci_misc.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MISC_H
-#define __MISC_H
-
-/* pin muxer definitions */
-#define PIN_MUX_NUM_FIELDS	8	/* Per register */
-#define PIN_MUX_FIELD_SIZE	4	/* n in bits */
-#define PIN_MUX_FIELD_MASK	((1 << PIN_MUX_FIELD_SIZE) - 1)
-
-/* pin definition */
-struct pinmux_config {
-	dv_reg		*mux;		/* Address of mux register */
-	unsigned char	value;		/* Value to set in field */
-	unsigned char	field;		/* field number */
-};
-
-/* pin table definition */
-struct pinmux_resource {
-	const struct pinmux_config	*pins;
-	const int 			n_pins;
-};
-
-#define PINMUX_ITEM(item) { \
-				.pins = item, \
-				.n_pins = ARRAY_SIZE(item) \
-			  }
-
-struct lpsc_resource {
-	const int	lpsc_no;
-};
-
-int dvevm_read_mac_address(uint8_t *buf);
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
-int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
-				    int n_items);
-#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
-void davinci_emac_mii_mode_sel(int mode_sel);
-#endif
-#if defined(CONFIG_SOC_DA8XX)
-void irq_init(void);
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
-				    const int n_items);
-#endif
-
-#endif /* __MISC_H */
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
deleted file mode 100644
index 24afd9d526..0000000000
--- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_DDR2_DEFS_H_
-#define _DV_DDR2_DEFS_H_
-
-/*
- * DDR2 Memory Ctrl Register structure
- * See sprueh7d.pdf for more details.
- */
-struct dv_ddr2_regs_ctrl {
-	unsigned char	rsvd0[4];	/* 0x00 */
-	unsigned int	sdrstat;	/* 0x04 */
-	unsigned int	sdbcr;		/* 0x08 */
-	unsigned int	sdrcr;		/* 0x0C */
-	unsigned int	sdtimr;		/* 0x10 */
-	unsigned int	sdtimr2;	/* 0x14 */
-	unsigned char	rsvd1[4];	/* 0x18 */
-	unsigned int	sdbcr2;		/* 0x1C */
-	unsigned int	pbbpr;		/* 0x20 */
-	unsigned char	rsvd2[156];	/* 0x24 */
-	unsigned int	irr;		/* 0xC0 */
-	unsigned int	imr;		/* 0xC4 */
-	unsigned int	imsr;		/* 0xC8 */
-	unsigned int	imcr;		/* 0xCC */
-	unsigned char	rsvd3[20];	/* 0xD0 */
-	unsigned int	ddrphycr;	/* 0xE4 */
-	unsigned int	ddrphycr2;	/* 0xE8 */
-	unsigned char	rsvd4[4];	/* 0xEC */
-};
-
-#define DV_DDR_PHY_PWRDNEN		0x40
-#define DV_DDR_PHY_EXT_STRBEN	0x80
-#define DV_DDR_PHY_RD_LATENCY_SHIFT	0
-
-#define DV_DDR_SDTMR1_RFC_SHIFT	25
-#define DV_DDR_SDTMR1_RP_SHIFT	22
-#define DV_DDR_SDTMR1_RCD_SHIFT	19
-#define DV_DDR_SDTMR1_WR_SHIFT	16
-#define DV_DDR_SDTMR1_RAS_SHIFT	11
-#define DV_DDR_SDTMR1_RC_SHIFT	6
-#define DV_DDR_SDTMR1_RRD_SHIFT	3
-#define DV_DDR_SDTMR1_WTR_SHIFT	0
-
-#define DV_DDR_SDTMR2_RASMAX_SHIFT	27
-#define DV_DDR_SDTMR2_XP_SHIFT	25
-#define DV_DDR_SDTMR2_ODT_SHIFT	23
-#define DV_DDR_SDTMR2_XSNR_SHIFT	16
-#define DV_DDR_SDTMR2_XSRD_SHIFT	8
-#define DV_DDR_SDTMR2_RTP_SHIFT	5
-#define DV_DDR_SDTMR2_CKE_SHIFT	0
-
-#define DV_DDR_SDCR_DDR2TERM1_SHIFT	27
-#define DV_DDR_SDCR_IBANK_POS_SHIFT	26
-#define DV_DDR_SDCR_MSDRAMEN_SHIFT	25
-#define DV_DDR_SDCR_DDRDRIVE1_SHIFT	24
-#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT	23
-#define DV_DDR_SDCR_DDR_DDQS_SHIFT	22
-#define DV_DDR_SDCR_DDR2EN_SHIFT	20
-#define DV_DDR_SDCR_DDRDRIVE0_SHIFT	18
-#define DV_DDR_SDCR_DDREN_SHIFT	17
-#define DV_DDR_SDCR_SDRAMEN_SHIFT	16
-#define DV_DDR_SDCR_TIMUNLOCK_SHIFT	15
-#define DV_DDR_SDCR_BUS_WIDTH_SHIFT	14
-#define DV_DDR_SDCR_CL_SHIFT		9
-#define DV_DDR_SDCR_IBANK_SHIFT	4
-#define DV_DDR_SDCR_PAGESIZE_SHIFT	0
-
-#define DV_DDR_SDRCR_LPMODEN	(1 << 31)
-#define DV_DDR_SDRCR_MCLKSTOPEN	(1 << 30)
-
-#define DV_DDR_SRCR_LPMODEN_SHIFT	31
-#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT	30
-
-#define DV_DDR_BOOTUNLOCK	(1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
-#define DV_DDR_TIMUNLOCK	(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
-
-#define dv_ddr2_regs_ctrl \
-	((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
-
-#endif /* _DV_DDR2_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
deleted file mode 100644
index 6c0275efa7..0000000000
--- a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __DM365_LOWLEVEL_H
-#define __DM365_LOWLEVEL_H
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-void dm365_waitloop(unsigned long loopcnt);
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
-int dm365_ddr_setup(void);
-void dm365_psc_init(void);
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
-	unsigned long value);
-void dm36x_lowlevel_init(ulong bootflag);
-
-#endif /* #ifndef __DM365_LOWLEVEL_H */
diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h
deleted file mode 100644
index c3f046efa8..0000000000
--- a/arch/arm/include/asm/arch-davinci/emac_defs.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Modifications:
- * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
- */
-
-#ifndef _DM644X_EMAC_H_
-#define _DM644X_EMAC_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM365
-#define EMAC_BASE_ADDR			(0x01d07000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
-#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
-#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
-#define DAVINCI_EMAC_VERSION2
-#elif defined(CONFIG_SOC_DA8XX)
-#define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
-#define EMAC_MDIO_BASE_ADDR		DAVINCI_MDIO_CNTRL_REGS_BASE
-#define DAVINCI_EMAC_VERSION2
-#else
-#define EMAC_BASE_ADDR			(0x01c80000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x01c81000)
-#define EMAC_WRAPPER_RAM_ADDR		(0x01c82000)
-#define EMAC_MDIO_BASE_ADDR		(0x01c84000)
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		76500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
-#elif defined(CONFIG_SOC_DM365)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		121500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
-#elif defined(CONFIG_SOC_DA8XX)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
-#else
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		99000000	/* PLL/6 - 99 MHz */
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
-#endif
-
-#define PHY_KSZ8873	(0x00221450)
-int ksz8873_is_phy_connected(int phy_addr);
-int ksz8873_get_link_speed(int phy_addr);
-int ksz8873_init_phy(int phy_addr);
-int ksz8873_auto_negotiate(int phy_addr);
-
-#define PHY_LXT972	(0x001378e2)
-int lxt972_is_phy_connected(int phy_addr);
-int lxt972_get_link_speed(int phy_addr);
-int lxt972_init_phy(int phy_addr);
-int lxt972_auto_negotiate(int phy_addr);
-
-#define PHY_DP83848	(0x20005c90)
-int dp83848_is_phy_connected(int phy_addr);
-int dp83848_get_link_speed(int phy_addr);
-int dp83848_init_phy(int phy_addr);
-int dp83848_auto_negotiate(int phy_addr);
-
-#define PHY_ET1011C	(0x282f013)
-int et1011c_get_link_speed(int phy_addr);
-
-#endif  /* _DM644X_EMAC_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h
deleted file mode 100644
index 7da0060cd4..0000000000
--- a/arch/arm/include/asm/arch-davinci/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _GPIO_DEFS_H_
-#define _GPIO_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define DAVINCI_GPIO_BINTEN	0x01C67008
-#define DAVINCI_GPIO_BANK01	0x01C67010
-#define DAVINCI_GPIO_BANK23	0x01C67038
-#define DAVINCI_GPIO_BANK45	0x01C67060
-#define DAVINCI_GPIO_BANK67	0x01C67088
-
-#else /* CONFIG_SOC_DA8XX */
-#define DAVINCI_GPIO_BINTEN	0x01E26008
-#define DAVINCI_GPIO_BANK01	0x01E26010
-#define DAVINCI_GPIO_BANK23	0x01E26038
-#define DAVINCI_GPIO_BANK45	0x01E26060
-#define DAVINCI_GPIO_BANK67	0x01E26088
-#define DAVINCI_GPIO_BANK8	0x01E260B0
-#endif /* CONFIG_SOC_DA8XX */
-
-struct davinci_gpio {
-	unsigned int dir;
-	unsigned int out_data;
-	unsigned int set_data;
-	unsigned int clr_data;
-	unsigned int in_data;
-	unsigned int set_rising;
-	unsigned int clr_rising;
-	unsigned int set_falling;
-	unsigned int clr_falling;
-	unsigned int intstat;
-};
-
-struct davinci_gpio_bank {
-	int num_gpio;
-	unsigned int irq_num;
-	unsigned int irq_mask;
-	unsigned long *in_use;
-	unsigned long base;
-};
-
-#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
-#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
-#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
-#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
-#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
-
-#define gpio_status()		gpio_info()
-#define GPIO_NAME_SIZE		20
-#if defined(CONFIG_SOC_DM644X)
-/* GPIO0 to GPIO53, omit the V3.3 volts one */
-#define MAX_NUM_GPIOS		70
-#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
-#define MAX_NUM_GPIOS		128
-#else
-#define MAX_NUM_GPIOS		144
-#endif
-#define GPIO_BANK(gp)		(davinci_gpio_bank01 + ((gp) >> 5))
-#define GPIO_BIT(gp)		((gp) & 0x1F)
-
-void gpio_info(void);
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
deleted file mode 100644
index a4eb0bd89b..0000000000
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ /dev/null
@@ -1,616 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * -------------------------------------------------------------------------
- *
- *  linux/include/asm-arm/arch-davinci/hardware.h
- *
- *  Copyright (C) 2006 Texas Instruments.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <config.h>
-#include <linux/sizes.h>
-
-#define	REG(addr)	(*(volatile unsigned int *)(addr))
-#define REG_P(addr)	((volatile unsigned int *)(addr))
-
-typedef volatile unsigned int	dv_reg;
-typedef volatile unsigned int *	dv_reg_p;
-
-/*
- * Base register addresses
- *
- * NOTE:  some of these DM6446-specific addresses DO NOT WORK
- * on other DaVinci chips.  Double check them before you try
- * using the addresses ... or PSC module identifiers, etc.
- */
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
-#define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
-#define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
-#define DAVINCI_UART0_BASE			(0x01c20000)
-#define DAVINCI_UART1_BASE			(0x01c20400)
-#define DAVINCI_TIMER3_BASE			(0x01c20800)
-#define DAVINCI_I2C_BASE			(0x01c21000)
-#define DAVINCI_TIMER0_BASE			(0x01c21400)
-#define DAVINCI_TIMER1_BASE			(0x01c21800)
-#define DAVINCI_WDOG_BASE			(0x01c21c00)
-#define DAVINCI_PWM0_BASE			(0x01c22000)
-#define DAVINCI_PWM1_BASE			(0x01c22400)
-#define DAVINCI_PWM2_BASE			(0x01c22800)
-#define DAVINCI_TIMER4_BASE			(0x01c23800)
-#define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
-#define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
-#define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
-#define DAVINCI_ARM_INTC_BASE			(0x01c48000)
-#define DAVINCI_USB_OTG_BASE			(0x01c64000)
-#define DAVINCI_CFC_ATA_BASE			(0x01c66000)
-#define DAVINCI_SPI_BASE			(0x01c66800)
-#define DAVINCI_GPIO_BASE			(0x01c67000)
-#define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
-#if !defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#endif
-#define DAVINCI_DDR_BASE			(0x80000000)
-
-#ifdef CONFIG_SOC_DM644X
-#define DAVINCI_UART2_BASE			0x01c20800
-#define DAVINCI_UHPI_BASE			0x01c67800
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
-#define DAVINCI_IMCOP_BASE			0x01cc0000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
-#define DAVINCI_VLYNQ_BASE			0x01e01000
-#define DAVINCI_ASP_BASE			0x01e02000
-#define DAVINCI_MMC_SD_BASE			0x01e10000
-#define DAVINCI_MS_BASE				0x01e20000
-#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
-
-#elif defined(CONFIG_SOC_DM355)
-#define DAVINCI_MMC_SD1_BASE			0x01e00000
-#define DAVINCI_ASP0_BASE			0x01e02000
-#define DAVINCI_ASP1_BASE			0x01e04000
-#define DAVINCI_UART2_BASE			0x01e06000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
-#define DAVINCI_MMC_SD0_BASE			0x01e11000
-
-#elif defined(CONFIG_SOC_DM365)
-#define DAVINCI_MMC_SD1_BASE			0x01d00000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
-#define DAVINCI_MMC_SD0_BASE			0x01d11000
-#define DAVINCI_DDR_EMIF_CTRL_BASE		0x20000000
-#define DAVINCI_SPI0_BASE			0x01c66000
-#define DAVINCI_SPI1_BASE			0x01c66800
-
-#elif defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	0x44000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x46000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
-
-#endif
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define DAVINCI_UART0_BASE			0x01c42000
-#define DAVINCI_UART1_BASE			0x01d0c000
-#define DAVINCI_UART2_BASE			0x01d0d000
-#define DAVINCI_I2C0_BASE			0x01c22000
-#define DAVINCI_I2C1_BASE			0x01e28000
-#define DAVINCI_TIMER0_BASE			0x01c20000
-#define DAVINCI_TIMER1_BASE			0x01c21000
-#define DAVINCI_WDOG_BASE			0x01c21000
-#define DAVINCI_RTC_BASE			0x01c23000
-#define DAVINCI_PLL_CNTRL0_BASE			0x01c11000
-#define DAVINCI_PLL_CNTRL1_BASE			0x01e1a000
-#define DAVINCI_PSC0_BASE			0x01c10000
-#define DAVINCI_PSC1_BASE			0x01e27000
-#define DAVINCI_SPI0_BASE			0x01c41000
-#define DAVINCI_USB_OTG_BASE			0x01e00000
-#define DAVINCI_SPI1_BASE			(cpu_is_da830() ? \
-						0x01e12000 : 0x01f0e000)
-#define DAVINCI_GPIO_BASE			0x01e26000
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01e23000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01e22000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01e20000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01e24000
-#define DAVINCI_SYSCFG1_BASE			0x01e2c000
-#define DAVINCI_MMC_SD0_BASE			0x01c40000
-#define DAVINCI_MMC_SD1_BASE			0x01e1b000
-#define DAVINCI_TIMER2_BASE			0x01f0c000
-#define DAVINCI_TIMER3_BASE			0x01f0d000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x68000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x40000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x60000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x62000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	0x64000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	0x66000000
-#define DAVINCI_DDR_EMIF_CTRL_BASE		0xb0000000
-#define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
-#define DAVINCI_INTC_BASE			0xfffee000
-#define DAVINCI_BOOTCFG_BASE			0x01c14000
-#define DAVINCI_LCD_CNTL_BASE			0x01e13000
-#define DAVINCI_L3CBARAM_BASE			0x80000000
-#define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
-#define CHIP_REV_ID_REG				(DAVINCI_BOOTCFG_BASE + 0x24)
-#define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
-#define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
-
-#define GPIO_BANK0_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x10)
-#define GPIO_BANK0_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x14)
-#define GPIO_BANK0_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x18)
-#define GPIO_BANK0_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x1c)
-#define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
-#define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
-#define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
-#define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
-#define GPIO_BANK6_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x88)
-#define GPIO_BANK6_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x8c)
-#define GPIO_BANK6_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x90)
-#define GPIO_BANK6_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x94)
-#endif /* CONFIG_SOC_DA8XX */
-
-/* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN		0
-#define DAVINCI_GPSC_DSPDOMAIN		1
-
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_LPSC_VPSSMSTR		0
-#define DAVINCI_LPSC_VPSSSLV		1
-#define DAVINCI_LPSC_TPCC		2
-#define DAVINCI_LPSC_TPTC0		3
-#define DAVINCI_LPSC_TPTC1		4
-#define DAVINCI_LPSC_EMAC		5
-#define DAVINCI_LPSC_EMAC_WRAPPER	6
-#define DAVINCI_LPSC_MDIO		7
-#define DAVINCI_LPSC_IEEE1394		8
-#define DAVINCI_LPSC_USB		9
-#define DAVINCI_LPSC_ATA		10
-#define DAVINCI_LPSC_VLYNQ		11
-#define DAVINCI_LPSC_UHPI		12
-#define DAVINCI_LPSC_DDR_EMIF		13
-#define DAVINCI_LPSC_AEMIF		14
-#define DAVINCI_LPSC_MMC_SD		15
-#define DAVINCI_LPSC_MEMSTICK		16
-#define DAVINCI_LPSC_McBSP		17
-#define DAVINCI_LPSC_I2C		18
-#define DAVINCI_LPSC_UART0		19
-#define DAVINCI_LPSC_UART1		20
-#define DAVINCI_LPSC_UART2		21
-#define DAVINCI_LPSC_SPI		22
-#define DAVINCI_LPSC_PWM0		23
-#define DAVINCI_LPSC_PWM1		24
-#define DAVINCI_LPSC_PWM2		25
-#define DAVINCI_LPSC_GPIO		26
-#define DAVINCI_LPSC_TIMER0		27
-#define DAVINCI_LPSC_TIMER1		28
-#define DAVINCI_LPSC_TIMER2		29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS	30
-#define DAVINCI_LPSC_ARM		31
-#define DAVINCI_LPSC_SCR2		32
-#define DAVINCI_LPSC_SCR3		33
-#define DAVINCI_LPSC_SCR4		34
-#define DAVINCI_LPSC_CROSSBAR		35
-#define DAVINCI_LPSC_CFG27		36
-#define DAVINCI_LPSC_CFG3		37
-#define DAVINCI_LPSC_CFG5		38
-#define DAVINCI_LPSC_GEM		39
-#define DAVINCI_LPSC_IMCOP		40
-#define DAVINCI_LPSC_VPSSMASTER		47
-#define DAVINCI_LPSC_MJCP		50
-#define DAVINCI_LPSC_HDVICP		51
-
-#define DAVINCI_DM646X_LPSC_EMAC	14
-#define DAVINCI_DM646X_LPSC_UART0	26
-#define DAVINCI_DM646X_LPSC_I2C		31
-#define DAVINCI_DM646X_LPSC_TIMER0	34
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define DAVINCI_LPSC_TPCC		0
-#define DAVINCI_LPSC_TPTC0		1
-#define DAVINCI_LPSC_TPTC1		2
-#define DAVINCI_LPSC_AEMIF		3
-#define DAVINCI_LPSC_SPI0		4
-#define DAVINCI_LPSC_MMC_SD		5
-#define DAVINCI_LPSC_AINTC		6
-#define DAVINCI_LPSC_ARM_RAM_ROM	7
-#define DAVINCI_LPSC_SECCTL_KEYMGR	8
-#define DAVINCI_LPSC_UART0		9
-#define DAVINCI_LPSC_SCR0		10
-#define DAVINCI_LPSC_SCR1		11
-#define DAVINCI_LPSC_SCR2		12
-#define DAVINCI_LPSC_DMAX		13
-#define DAVINCI_LPSC_ARM		14
-#define DAVINCI_LPSC_GEM		15
-
-/* for LPSCs in PSC1, offset from 32 for differentiation */
-#define DAVINCI_LPSC_PSC1_BASE		32
-#define DAVINCI_LPSC_USB20		(DAVINCI_LPSC_PSC1_BASE + 1)
-#define DAVINCI_LPSC_USB11		(DAVINCI_LPSC_PSC1_BASE + 2)
-#define DAVINCI_LPSC_GPIO		(DAVINCI_LPSC_PSC1_BASE + 3)
-#define DAVINCI_LPSC_UHPI		(DAVINCI_LPSC_PSC1_BASE + 4)
-#define DAVINCI_LPSC_EMAC		(DAVINCI_LPSC_PSC1_BASE + 5)
-#define DAVINCI_LPSC_DDR_EMIF		(DAVINCI_LPSC_PSC1_BASE + 6)
-#define DAVINCI_LPSC_McASP0		(DAVINCI_LPSC_PSC1_BASE + 7)
-#define DAVINCI_LPSC_SPI1		(DAVINCI_LPSC_PSC1_BASE + 10)
-#define DAVINCI_LPSC_I2C1		(DAVINCI_LPSC_PSC1_BASE + 11)
-#define DAVINCI_LPSC_UART1		(DAVINCI_LPSC_PSC1_BASE + 12)
-#define DAVINCI_LPSC_UART2		(DAVINCI_LPSC_PSC1_BASE + 13)
-#define DAVINCI_LPSC_LCDC		(DAVINCI_LPSC_PSC1_BASE + 16)
-#define DAVINCI_LPSC_ePWM		(DAVINCI_LPSC_PSC1_BASE + 17)
-#define DAVINCI_LPSC_MMCSD1		(DAVINCI_LPSC_PSC1_BASE + 18)
-#define DAVINCI_LPSC_eCAP		(DAVINCI_LPSC_PSC1_BASE + 20)
-#define DAVINCI_LPSC_L3_CBA_RAM		(DAVINCI_LPSC_PSC1_BASE + 31)
-
-/* DA830-specific peripherals */
-#define DAVINCI_LPSC_McASP1		(DAVINCI_LPSC_PSC1_BASE + 8)
-#define DAVINCI_LPSC_McASP2		(DAVINCI_LPSC_PSC1_BASE + 9)
-#define DAVINCI_LPSC_eQEP		(DAVINCI_LPSC_PSC1_BASE + 21)
-#define DAVINCI_LPSC_SCR8		(DAVINCI_LPSC_PSC1_BASE + 24)
-#define DAVINCI_LPSC_SCR7		(DAVINCI_LPSC_PSC1_BASE + 25)
-#define DAVINCI_LPSC_SCR12		(DAVINCI_LPSC_PSC1_BASE + 26)
-
-/* DA850-specific peripherals */
-#define DAVINCI_LPSC_TPCC1		(DAVINCI_LPSC_PSC1_BASE + 0)
-#define DAVINCI_LPSC_SATA		(DAVINCI_LPSC_PSC1_BASE + 8)
-#define DAVINCI_LPSC_VPIF		(DAVINCI_LPSC_PSC1_BASE + 9)
-#define DAVINCI_LPSC_McBSP0		(DAVINCI_LPSC_PSC1_BASE + 14)
-#define DAVINCI_LPSC_McBSP1		(DAVINCI_LPSC_PSC1_BASE + 15)
-#define DAVINCI_LPSC_MMC_SD1		(DAVINCI_LPSC_PSC1_BASE + 18)
-#define DAVINCI_LPSC_uPP		(DAVINCI_LPSC_PSC1_BASE + 19)
-#define DAVINCI_LPSC_TPTC2		(DAVINCI_LPSC_PSC1_BASE + 21)
-#define DAVINCI_LPSC_SCR_F0		(DAVINCI_LPSC_PSC1_BASE + 24)
-#define DAVINCI_LPSC_SCR_F1		(DAVINCI_LPSC_PSC1_BASE + 25)
-#define DAVINCI_LPSC_SCR_F2		(DAVINCI_LPSC_PSC1_BASE + 26)
-#define DAVINCI_LPSC_SCR_F6		(DAVINCI_LPSC_PSC1_BASE + 27)
-#define DAVINCI_LPSC_SCR_F7		(DAVINCI_LPSC_PSC1_BASE + 28)
-#define DAVINCI_LPSC_SCR_F8		(DAVINCI_LPSC_PSC1_BASE + 29)
-#define DAVINCI_LPSC_BR_F7		(DAVINCI_LPSC_PSC1_BASE + 30)
-
-#endif /* CONFIG_SOC_DA8XX */
-
-void lpsc_on(unsigned int id);
-void lpsc_syncreset(unsigned int id);
-void lpsc_disable(unsigned int id);
-void dsp_on(void);
-
-void davinci_enable_uart0(void);
-void davinci_enable_emac(void);
-void davinci_enable_i2c(void);
-void davinci_errata_workarounds(void);
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Some PSC defines */
-#define PSC_CHP_SHRTSW			(0x01c40038)
-#define PSC_GBLCTL			(0x01c41010)
-#define PSC_EPCPR			(0x01c41070)
-#define PSC_EPCCR			(0x01c41078)
-#define PSC_PTCMD			(0x01c41120)
-#define PSC_PTSTAT			(0x01c41128)
-#define PSC_PDSTAT			(0x01c41200)
-#define PSC_PDSTAT1			(0x01c41204)
-#define PSC_PDCTL			(0x01c41300)
-#define PSC_PDCTL1			(0x01c41304)
-
-#define PSC_MDCTL_BASE			(0x01c41a00)
-#define PSC_MDSTAT_BASE			(0x01c41800)
-
-#define VDD3P3V_PWDN			(0x01c40048)
-#define UART0_PWREMU_MGMT		(0x01c20030)
-
-#define PSC_SILVER_BULLET		(0x01c41a20)
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define	PSC_ENABLE		0x3
-#define	PSC_DISABLE		0x2
-#define	PSC_SYNCRESET		0x1
-#define	PSC_SWRSTDISABLE	0x0
-
-#define PSC_PSC0_MODULE_ID_CNT		16
-#define PSC_PSC1_MODULE_ID_CNT		32
-
-#define UART0_PWREMU_MGMT		(0x01c42030)
-
-struct davinci_psc_regs {
-	dv_reg	revid;
-	dv_reg	rsvd0[71];
-	dv_reg	ptcmd;
-	dv_reg	rsvd1;
-	dv_reg	ptstat;
-	dv_reg	rsvd2[437];
-	union {
-		struct {
-			dv_reg	mdstat[PSC_PSC0_MODULE_ID_CNT];
-			dv_reg	rsvd3[112];
-			dv_reg	mdctl[PSC_PSC0_MODULE_ID_CNT];
-		} psc0;
-		struct {
-			dv_reg	mdstat[PSC_PSC1_MODULE_ID_CNT];
-			dv_reg	rsvd3[96];
-			dv_reg	mdctl[PSC_PSC1_MODULE_ID_CNT];
-		} psc1;
-	};
-};
-
-#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
-#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#define PSC_MDSTAT_STATE		0x3f
-#define PSC_MDCTL_NEXT			0x07
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Miscellania... */
-#define VBPR				(0x20000020)
-
-/* NOTE:  system control modules are *highly* chip-specific, both
- * as to register content (e.g. for muxing) and which registers exist.
- */
-#define PINMUX0				0x01c40000
-#define PINMUX1				0x01c40004
-#define PINMUX2				0x01c40008
-#define PINMUX3				0x01c4000c
-#define PINMUX4				0x01c40010
-
-struct davinci_uart_ctrl_regs {
-	dv_reg	revid1;
-	dv_reg	res;
-	dv_reg	pwremu_mgmt;
-	dv_reg	mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
-
-#else /* CONFIG_SOC_DA8XX */
-
-struct davinci_pllc_regs {
-	dv_reg	revid;
-	dv_reg	rsvd1[56];
-	dv_reg	rstype;
-	dv_reg	rsvd2[6];
-	dv_reg	pllctl;
-	dv_reg	ocsel;
-	dv_reg	rsvd3[2];
-	dv_reg	pllm;
-	dv_reg	prediv;
-	dv_reg	plldiv1;
-	dv_reg	plldiv2;
-	dv_reg	plldiv3;
-	dv_reg	oscdiv;
-	dv_reg	postdiv;
-	dv_reg	rsvd4[3];
-	dv_reg	pllcmd;
-	dv_reg	pllstat;
-	dv_reg	alnctl;
-	dv_reg	dchange;
-	dv_reg	cken;
-	dv_reg	ckstat;
-	dv_reg	systat;
-	dv_reg	rsvd5[3];
-	dv_reg	plldiv4;
-	dv_reg	plldiv5;
-	dv_reg	plldiv6;
-	dv_reg	plldiv7;
-	dv_reg	rsvd6[32];
-	dv_reg	emucnt0;
-	dv_reg	emucnt1;
-};
-
-#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
-#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
-#define DAVINCI_PLLC_DIV_MASK	0x1f
-
-/*
- * A clock ID is a 32-bit number where bit 16 represents the PLL controller
- * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
- * counting from 1. Clock IDs may be passed to clk_get().
- */
-
-/* flags to select PLL controller */
-#define DAVINCI_PLLC0_FLAG			(0)
-#define DAVINCI_PLLC1_FLAG			(1 << 16)
-
-enum davinci_clk_ids {
-	/*
-	 * Clock IDs for PLL outputs. Each may be switched on/off
-	 * independently, and each may map to one or more peripherals.
-	 */
-	DAVINCI_PLL0_SYSCLK2			= DAVINCI_PLLC0_FLAG | 2,
-	DAVINCI_PLL0_SYSCLK4			= DAVINCI_PLLC0_FLAG | 4,
-	DAVINCI_PLL0_SYSCLK6			= DAVINCI_PLLC0_FLAG | 6,
-	DAVINCI_PLL1_SYSCLK1			= DAVINCI_PLLC1_FLAG | 1,
-	DAVINCI_PLL1_SYSCLK2			= DAVINCI_PLLC1_FLAG | 2,
-
-	/* map peripherals to clock IDs */
-	DAVINCI_ARM_CLKID			= DAVINCI_PLL0_SYSCLK6,
-	DAVINCI_DDR_CLKID			= DAVINCI_PLL1_SYSCLK1,
-	DAVINCI_MDIO_CLKID			= DAVINCI_PLL0_SYSCLK4,
-	DAVINCI_MMC_CLKID			= DAVINCI_PLL0_SYSCLK2,
-	DAVINCI_SPI0_CLKID			= DAVINCI_PLL0_SYSCLK2,
-	DAVINCI_MMCSD_CLKID			= DAVINCI_PLL0_SYSCLK2,
-
-	/* special clock ID - output of PLL multiplier */
-	DAVINCI_PLLM_CLKID			= 0x0FF,
-
-	/* special clock ID - output of PLL post divisor */
-	DAVINCI_PLLC_CLKID			= 0x100,
-
-	/* special clock ID - PLL bypass */
-	DAVINCI_AUXCLK_CLKID			= 0x101,
-};
-
-#define DAVINCI_UART2_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
-						: get_async3_src())
-
-#define DAVINCI_SPI1_CLKID	(cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
-						: get_async3_src())
-
-int clk_get(enum davinci_clk_ids id);
-
-/* Boot config */
-struct davinci_syscfg_regs {
-	dv_reg	revid;
-	dv_reg	rsvd[13];
-	dv_reg	kick0;
-	dv_reg	kick1;
-	dv_reg	rsvd1[52];
-	dv_reg	mstpri[3];
-	dv_reg  rsvd2;
-	dv_reg	pinmux[20];
-	dv_reg	suspsrc;
-	dv_reg	chipsig;
-	dv_reg	chipsig_clr;
-	dv_reg	cfgchip0;
-	dv_reg	cfgchip1;
-	dv_reg	cfgchip2;
-	dv_reg	cfgchip3;
-	dv_reg	cfgchip4;
-};
-
-#define davinci_syscfg_regs \
-	((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
-
-#define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
-
-/* Emulation suspend bits */
-#define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
-#define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART0		(1 << 18)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
-#define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
-
-struct davinci_syscfg1_regs {
-	dv_reg	vtpio_ctl;
-	dv_reg	ddr_slew;
-	dv_reg	deepsleep;
-	dv_reg	pupd_ena;
-	dv_reg	pupd_sel;
-	dv_reg	rxactive;
-	dv_reg	pwrdwn;
-};
-
-#define davinci_syscfg1_regs \
-	((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
-
-#define DDR_SLEW_CMOSEN_BIT	4
-#define DDR_SLEW_DDR_PDENA_BIT	5
-
-#define VTP_POWERDWN		(1 << 6)
-#define VTP_LOCK		(1 << 7)
-#define VTP_CLKRZ		(1 << 13)
-#define VTP_READY		(1 << 15)
-#define VTP_IOPWRDWN		(1 << 14)
-
-#define DV_SYSCFG_KICK0_UNLOCK	0x83e70b13
-#define DV_SYSCFG_KICK1_UNLOCK	0x95a4f1e0
-
-/* Interrupt controller */
-struct davinci_aintc_regs {
-	dv_reg	revid;
-	dv_reg	cr;
-	dv_reg	dummy0[2];
-	dv_reg	ger;
-	dv_reg	dummy1[219];
-	dv_reg	ecr1;
-	dv_reg	ecr2;
-	dv_reg	ecr3;
-	dv_reg	dummy2[1117];
-	dv_reg	hier;
-};
-
-#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
-
-struct davinci_uart_ctrl_regs {
-	dv_reg	revid1;
-	dv_reg	revid2;
-	dv_reg	pwremu_mgmt;
-	dv_reg	mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
-
-#define davinci_uart0_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
-#define davinci_uart1_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
-#define davinci_uart2_ctrl_regs \
-	((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
-
-static inline int cpu_is_da830(void)
-{
-	unsigned int jtag_id	= REG(JTAG_ID_REG);
-	unsigned short part_no	= (jtag_id >> 12) & 0xffff;
-
-	return ((part_no == 0xb7df) ? 1 : 0);
-}
-static inline int cpu_is_da850(void)
-{
-	unsigned int jtag_id    = REG(JTAG_ID_REG);
-	unsigned short part_no  = (jtag_id >> 12) & 0xffff;
-
-	return ((part_no == 0xb7d1) ? 1 : 0);
-}
-
-static inline enum davinci_clk_ids get_async3_src(void)
-{
-	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
-			DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
-}
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#if defined(CONFIG_SOC_DM365)
-#include <asm/arch/aintc_defs.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pll_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/syscfg_defs.h>
-#include <asm/arch/timer_defs.h>
-
-#define TMPBUF			0x00017ff8
-#define TMPSTATUS		0x00017ff0
-#define DV_TMPBUF_VAL		0x591b3ed7
-#define FLAG_PORRST		0x00000001
-#define FLAG_WDTRST		0x00000002
-#define FLAG_FLGON		0x00000004
-#define FLAG_FLGOFF		0x00000010
-
-#endif
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/include/asm/arch-davinci/i2c_defs.h
deleted file mode 100644
index 06da8947b4..0000000000
--- a/arch/arm/include/asm/arch-davinci/i2c_defs.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004-2014
- * Texas Instruments, <www.ti.com>
- *
- * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _I2C_DEFS_H_
-#define _I2C_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define I2C_BASE		0x01c21000
-#else
-#define I2C_BASE		0x01c22000
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
deleted file mode 100644
index 2d82af554b..0000000000
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Pinmux configurations for the DAxxx SoCs
- *
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_PINMUX_DEFS_H
-#define __ASM_ARCH_PINMUX_DEFS_H
-
-#include <asm/arch/davinci_misc.h>
-#include <config.h>
-
-/* SPI0 pin muxer settings */
-extern const struct pinmux_config spi0_pins_base[3];
-extern const struct pinmux_config spi0_pins_scs0[1];
-extern const struct pinmux_config spi0_pins_ena[1];
-
-/* SPI1 pin muxer settings */
-extern const struct pinmux_config spi1_pins_base[3];
-extern const struct pinmux_config spi1_pins_scs0[1];
-
-/* UART pin muxer settings */
-extern const struct pinmux_config uart0_pins_txrx[2];
-extern const struct pinmux_config uart0_pins_rtscts[2];
-extern const struct pinmux_config uart1_pins_txrx[2];
-extern const struct pinmux_config uart2_pins_txrx[2];
-extern const struct pinmux_config uart2_pins_rtscts[2];
-
-/* EMAC pin muxer settings*/
-extern const struct pinmux_config emac_pins_rmii[8];
-extern const struct pinmux_config emac_pins_rmii_clk_source[1];
-extern const struct pinmux_config emac_pins_mii[15];
-extern const struct pinmux_config emac_pins_mdio[2];
-
-/* I2C pin muxer settings */
-extern const struct pinmux_config i2c0_pins[2];
-extern const struct pinmux_config i2c1_pins[2];
-
-/* EMIFA pin muxer settings */
-extern const struct pinmux_config emifa_pins[40];
-extern const struct pinmux_config emifa_pins_cs0[1];
-extern const struct pinmux_config emifa_pins_cs2[1];
-extern const struct pinmux_config emifa_pins_cs3[1];
-extern const struct pinmux_config emifa_pins_cs4[1];
-extern const struct pinmux_config emifa_pins_nand[12];
-extern const struct pinmux_config emifa_pins_nor[43];
-
-/* USB pin mux setting */
-extern const struct pinmux_config usb_pins[1];
-
-/* MMC pin muxer settings */
-extern const struct pinmux_config mmc0_pins_8bit[10];
-extern const struct pinmux_config mmc0_pins[6];
-
-#endif
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
deleted file mode 100644
index d083cccadb..0000000000
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_PLL_DEFS_H_
-#define _DV_PLL_DEFS_H_
-
-struct dv_pll_regs {
-	unsigned int	pid;		/* 0x00 */
-	unsigned char	rsvd0[224];	/* 0x04 */
-	unsigned int	rstype;		/* 0xe4 */
-	unsigned char	rsvd1[24];	/* 0xe8 */
-	unsigned int	pllctl;		/* 0x100 */
-	unsigned char	rsvd2[4];	/* 0x104 */
-	unsigned int	secctl;		/* 0x108 */
-	unsigned int	rv;		/* 0x10c */
-	unsigned int	pllm;		/* 0x110 */
-	unsigned int	prediv;		/* 0x114 */
-	unsigned int	plldiv1;	/* 0x118 */
-	unsigned int	plldiv2;	/* 0x11c */
-	unsigned int	plldiv3;	/* 0x120 */
-	unsigned int	oscdiv1;	/* 0x124 */
-	unsigned int	postdiv;	/* 0x128 */
-	unsigned int	bpdiv;		/* 0x12c */
-	unsigned char	rsvd5[8];	/* 0x130 */
-	unsigned int	pllcmd;		/* 0x138 */
-	unsigned int	pllstat;	/* 0x13c */
-	unsigned int	alnctl;		/* 0x140 */
-	unsigned int	dchange;	/* 0x144 */
-	unsigned int	cken;		/* 0x148 */
-	unsigned int	ckstat;		/* 0x14c */
-	unsigned int	systat;		/* 0x150 */
-	unsigned char	rsvd6[12];	/* 0x154 */
-	unsigned int	plldiv4;	/* 0x160 */
-	unsigned int	plldiv5;	/* 0x164 */
-	unsigned int	plldiv6;	/* 0x168 */
-	unsigned int	plldiv7;	/* 0x16C */
-	unsigned int	plldiv8;	/* 0x170 */
-	unsigned int	plldiv9;	/* 0x174 */
-};
-
-#define PLL_MASTER_LOCK	(1 << 4)
-
-#define PLLCTL_CLOCK_MODE_SHIFT	8
-#define PLLCTL_PLLEN	(1 << 0)
-#define PLLCTL_PLLPWRDN	(1 << 1)
-#define PLLCTL_PLLRST	(1 << 3)
-#define PLLCTL_PLLDIS	(1 << 4)
-#define PLLCTL_PLLENSRC	(1 << 5)
-#define PLLCTL_RES_9	(1 << 8)
-#define PLLCTL_EXTCLKSRC	(1 << 9)
-
-#define PLL_DIVEN	(1 << 15)
-#define PLL_POSTDEN	PLL_DIVEN
-
-#define PLL_SCSCFG3_DIV45PENA	(1 << 2)
-#define PLL_SCSCFG3_EMA_CLKSRC	(1 << 1)
-
-#define PLL_RSTYPE_POR		(1 << 0)
-#define PLL_RSTYPE_XWRST	(1 << 1)
-
-#define PLLSECCTL_TINITZ	(1 << 16)
-#define PLLSECCTL_TENABLE	(1 << 17)
-#define PLLSECCTL_TENABLEDIV	(1 << 18)
-#define PLLSECCTL_STOPMODE	(1 << 22)
-
-#define PLLCMD_GOSET		(1 << 0)
-#define PLLCMD_GOSTAT		(1 << 0)
-
-#define PLL0_LOCK		0x07000000
-#define PLL1_LOCK		0x07000000
-
-#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
-#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
-
-#define ARM_PLLDIV	(offsetof(struct dv_pll_regs, plldiv2))
-#define DDR_PLLDIV	(offsetof(struct dv_pll_regs, plldiv7))
-#define SPI_PLLDIV	(offsetof(struct dv_pll_regs, plldiv4))
-
-unsigned int davinci_clk_get(unsigned int div);
-#endif /* _DV_PLL_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/include/asm/arch-davinci/psc_defs.h
deleted file mode 100644
index bcb5580499..0000000000
--- a/arch/arm/include/asm/arch-davinci/psc_defs.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_PSC_DEFS_H_
-#define _DV_PSC_DEFS_H_
-
-/*
- * Power/Sleep Ctrl Register structure
- * See sprufb3.pdf, Chapter 7
- */
-struct dv_psc_regs {
-	unsigned int	pid;		/* 0x000 */
-	unsigned char	rsvd0[16];	/* 0x004 */
-	unsigned char	rsvd1[4];	/* 0x014 */
-	unsigned int	inteval;	/* 0x018 */
-	unsigned char	rsvd2[36];	/* 0x01C */
-	unsigned int	merrpr0;	/* 0x040 */
-	unsigned int	merrpr1;	/* 0x044 */
-	unsigned char	rsvd3[8];	/* 0x048 */
-	unsigned int	merrcr0;	/* 0x050 */
-	unsigned int	merrcr1;	/* 0x054 */
-	unsigned char	rsvd4[8];	/* 0x058 */
-	unsigned int	perrpr;		/* 0x060 */
-	unsigned char	rsvd5[4];	/* 0x064 */
-	unsigned int	perrcr;		/* 0x068 */
-	unsigned char	rsvd6[4];	/* 0x06C */
-	unsigned int	epcpr;		/* 0x070 */
-	unsigned char	rsvd7[4];	/* 0x074 */
-	unsigned int	epccr;		/* 0x078 */
-	unsigned char	rsvd8[144];	/* 0x07C */
-	unsigned char	rsvd9[20];	/* 0x10C */
-	unsigned int	ptcmd;		/* 0x120 */
-	unsigned char	rsvd10[4];	/* 0x124 */
-	unsigned int	ptstat;		/* 0x128 */
-	unsigned char	rsvd11[212];	/* 0x12C */
-	unsigned int	pdstat0;	/* 0x200 */
-	unsigned int	pdstat1;	/* 0x204 */
-	unsigned char	rsvd12[248];	/* 0x208 */
-	unsigned int	pdctl0;		/* 0x300 */
-	unsigned int	pdctl1;		/* 0x304 */
-	unsigned char	rsvd13[536];	/* 0x308 */
-	unsigned int	mckout0;	/* 0x520 */
-	unsigned int	mckout1;	/* 0x524 */
-	unsigned char	rsvd14[728];	/* 0x528 */
-	unsigned int	mdstat[52];	/* 0x800 */
-	unsigned char	rsvd15[304];	/* 0x8D0 */
-	unsigned int	mdctl[52];	/* 0xA00 */
-};
-
-/* PSC constants */
-#define EMURSTIE_MASK	(0x00000200)
-
-#define PD0		(0)
-
-#define PSC_ENABLE		(0x3)
-#define PSC_DISABLE		(0x2)
-#define PSC_SYNCRESET		(0x1)
-#define PSC_SWRSTDISABLE	(0x0)
-
-#define PSC_GOSTAT		(1 << 0)
-#define PSC_MD_STATE_MSK	(0x1f)
-
-#define PSC_CMD_GO		(1 << 0)
-
-#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
-
-#endif /* _DV_PSC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
deleted file mode 100644
index 9aa3f4ab27..0000000000
--- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
- *
- * Copyright (C) 2010 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SDMMC_DEFS_H_
-#define _SDMMC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-/* MMC Control Reg fields */
-#define MMCCTL_DATRST		(1 << 0)
-#define MMCCTL_CMDRST		(1 << 1)
-#define MMCCTL_WIDTH_4_BIT	(1 << 2)
-#define MMCCTL_DATEG_DISABLED	(0 << 6)
-#define MMCCTL_DATEG_RISING	(1 << 6)
-#define MMCCTL_DATEG_FALLING	(2 << 6)
-#define MMCCTL_DATEG_BOTH	(3 << 6)
-#define MMCCTL_PERMDR_LE	(0 << 9)
-#define MMCCTL_PERMDR_BE	(1 << 9)
-#define MMCCTL_PERMDX_LE	(0 << 10)
-#define MMCCTL_PERMDX_BE	(1 << 10)
-
-/* MMC Clock Control Reg fields */
-#define MMCCLK_CLKEN		(1 << 8)
-#define MMCCLK_CLKRT_MASK	(0xFF << 0)
-
-/* MMC Status Reg0 fields */
-#define MMCST0_DATDNE		(1 << 0)
-#define MMCST0_BSYDNE		(1 << 1)
-#define MMCST0_RSPDNE		(1 << 2)
-#define MMCST0_TOUTRD		(1 << 3)
-#define MMCST0_TOUTRS		(1 << 4)
-#define MMCST0_CRCWR		(1 << 5)
-#define MMCST0_CRCRD		(1 << 6)
-#define MMCST0_CRCRS		(1 << 7)
-#define MMCST0_DXRDY		(1 << 9)
-#define MMCST0_DRRDY		(1 << 10)
-#define MMCST0_DATED		(1 << 11)
-#define MMCST0_TRNDNE		(1 << 12)
-
-#define MMCST0_ERR_MASK		(0x00F8)
-
-/* MMC Status Reg1 fields */
-#define MMCST1_BUSY		(1 << 0)
-#define MMCST1_CLKSTP		(1 << 1)
-#define MMCST1_DXEMP		(1 << 2)
-#define MMCST1_DRFUL		(1 << 3)
-#define MMCST1_DAT3ST		(1 << 4)
-#define MMCST1_FIFOEMP		(1 << 5)
-#define MMCST1_FIFOFUL		(1 << 6)
-
-/* MMC INT Mask Reg fields */
-#define MMCIM_EDATDNE		(1 << 0)
-#define MMCIM_EBSYDNE		(1 << 1)
-#define MMCIM_ERSPDNE		(1 << 2)
-#define MMCIM_ETOUTRD		(1 << 3)
-#define MMCIM_ETOUTRS		(1 << 4)
-#define MMCIM_ECRCWR		(1 << 5)
-#define MMCIM_ECRCRD		(1 << 6)
-#define MMCIM_ECRCRS		(1 << 7)
-#define MMCIM_EDXRDY		(1 << 9)
-#define MMCIM_EDRRDY		(1 << 10)
-#define MMCIM_EDATED		(1 << 11)
-#define MMCIM_ETRNDNE		(1 << 12)
-
-#define MMCIM_MASKALL		(0xFFFFFFFF)
-
-/* MMC Resp Tout Reg fields */
-#define MMCTOR_TOR_MASK		(0xFF)		/* dont write to reg, | it */
-#define MMCTOR_TOD_20_16_SHIFT  (8)
-
-/* MMC Data Read Tout Reg fields */
-#define MMCTOD_TOD_0_15_MASK	(0xFFFF)
-
-/* MMC Block len Reg fields */
-#define MMCBLEN_BLEN_MASK	(0xFFF)
-
-/* MMC Num Blocks Reg fields */
-#define MMCNBLK_NBLK_MASK	(0xFFFF)
-#define MMCNBLK_NBLK_MAX	(0xFFFF)
-
-/* MMC Num Blocks Counter Reg fields */
-#define MMCNBLC_NBLC_MASK	(0xFFFF)
-
-/* MMC Cmd Reg fields */
-#define MMCCMD_CMD_MASK		(0x3F)
-#define MMCCMD_PPLEN		(1 << 7)
-#define MMCCMD_BSYEXP		(1 << 8)
-#define MMCCMD_RSPFMT_NONE	(0 << 9)
-#define MMCCMD_RSPFMT_R1567	(1 << 9)
-#define MMCCMD_RSPFMT_R2	(2 << 9)
-#define MMCCMD_RSPFMT_R3	(3 << 9)
-#define MMCCMD_DTRW		(1 << 11)
-#define MMCCMD_STRMTP		(1 << 12)
-#define MMCCMD_WDATX		(1 << 13)
-#define MMCCMD_INITCK		(1 << 14)
-#define MMCCMD_DCLR		(1 << 15)
-#define MMCCMD_DMATRIG		(1 << 16)
-
-/* FIFO control Reg fields */
-#define MMCFIFOCTL_FIFORST	(1 << 0)
-#define MMCFIFOCTL_FIFODIR	(1 << 1)
-#define MMCFIFOCTL_FIFOLEV	(1 << 2)
-#define MMCFIFOCTL_ACCWD_4	(0 << 3)	/* access width of 4 bytes */
-#define MMCFIFOCTL_ACCWD_3	(1 << 3)	/* access width of 3 bytes */
-#define MMCFIFOCTL_ACCWD_2	(2 << 3)	/* access width of 2 bytes */
-#define MMCFIFOCTL_ACCWD_1	(3 << 3)	/* access width of 1 byte */
-
-/* Davinci MMC Register definitions */
-struct davinci_mmc_regs {
-	dv_reg mmcctl;
-	dv_reg mmcclk;
-	dv_reg mmcst0;
-	dv_reg mmcst1;
-	dv_reg mmcim;
-	dv_reg mmctor;
-	dv_reg mmctod;
-	dv_reg mmcblen;
-	dv_reg mmcnblk;
-	dv_reg mmcnblc;
-	dv_reg mmcdrr;
-	dv_reg mmcdxr;
-	dv_reg mmccmd;
-	dv_reg mmcarghl;
-	dv_reg mmcrsp01;
-	dv_reg mmcrsp23;
-	dv_reg mmcrsp45;
-	dv_reg mmcrsp67;
-	dv_reg mmcdrsp;
-	dv_reg mmcetok;
-	dv_reg mmccidx;
-	dv_reg mmcckc;
-	dv_reg mmctorc;
-	dv_reg mmctodc;
-	dv_reg mmcblnc;
-	dv_reg sdioctl;
-	dv_reg sdiost0;
-	dv_reg sdioien;
-	dv_reg sdioist;
-	dv_reg mmcfifoctl;
-};
-
-/* Davinci MMC board definitions */
-struct davinci_mmc {
-	struct davinci_mmc_regs *reg_base;	/* Register base address */
-	uint input_clk;		/* Input clock to MMC controller */
-	uint host_caps;		/* Host capabilities */
-	uint voltages;		/* Host supported voltages */
-	uint version;		/* MMC Controller version */
-	struct mmc_config cfg;
-};
-
-enum {
-	MMC_CTLR_VERSION_1 = 0,	/* DM644x and DM355 */
-	MMC_CTLR_VERSION_2,	/* DA830 */
-};
-
-int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
-
-#endif /* _SDMMC_DEFS_H */
diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/include/asm/arch-davinci/syscfg_defs.h
deleted file mode 100644
index 812088f379..0000000000
--- a/arch/arm/include/asm/arch-davinci/syscfg_defs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_SYSCFG_DEFS_H_
-#define _DV_SYSCFG_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-/* System Control Module register structure for DM365 */
-struct dv_sys_module_regs {
-	unsigned int	pinmux[5];	/* 0x00 */
-	unsigned int	bootcfg;	/* 0x14 */
-	unsigned int	arm_intmux;	/* 0x18 */
-	unsigned int	edma_evtmux;	/* 0x1C */
-	unsigned int	ddr_slew;	/* 0x20 */
-	unsigned int	clkout;		/* 0x24 */
-	unsigned int	device_id;	/* 0x28 */
-	unsigned int	vdac_config;	/* 0x2C */
-	unsigned int	timer64_ctl;	/* 0x30 */
-	unsigned int	usbbphy_ctl;	/* 0x34 */
-	unsigned int	misc;		/* 0x38 */
-	unsigned int	mstpri[2];	/* 0x3C */
-	unsigned int	vpss_clkctl;	/* 0x44 */
-	unsigned int	peri_clkctl;	/* 0x48 */
-	unsigned int	deepsleep;	/* 0x4C */
-	unsigned int	dft_enable;	/* 0x50 */
-	unsigned int	debounce[8];	/* 0x54 */
-	unsigned int	vtpiocr;	/* 0x74 */
-	unsigned int	pupdctl0;	/* 0x78 */
-	unsigned int	pupdctl1;	/* 0x7C */
-	unsigned int	hdimcopbt;	/* 0x80 */
-	unsigned int	pll0_config;	/* 0x84 */
-	unsigned int	pll1_config;	/* 0x88 */
-};
-
-#define VPTIO_RDY	(1 << 15)
-#define VPTIO_IOPWRDN	(1 << 14)
-#define VPTIO_CLRZ	(1 << 13)
-#define VPTIO_LOCK	(1 << 7)
-#define VPTIO_PWRDN	(1 << 6)
-
-#define VPSS_CLK_CTL_VPSS_CLKMD	(1 << 7)
-
-#define dv_sys_module_regs \
-	((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
-
-#endif /* !CONFIG_SOC_DA8XX */
-#endif /* _DV_SYSCFG_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/timer_defs.h b/arch/arm/include/asm/arch-davinci/timer_defs.h
deleted file mode 100644
index 94d18320d9..0000000000
--- a/arch/arm/include/asm/arch-davinci/timer_defs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 DENX Software Engineering GmbH
- * Heiko Schocher <hs@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _TIMER_DEFS_H_
-#define _TIMER_DEFS_H_
-
-struct davinci_timer {
-	u_int32_t	pid12;
-	u_int32_t	emumgt;
-	u_int32_t	na1;
-	u_int32_t	na2;
-	u_int32_t	tim12;
-	u_int32_t	tim34;
-	u_int32_t	prd12;
-	u_int32_t	prd34;
-	u_int32_t	tcr;
-	u_int32_t	tgcr;
-	u_int32_t	wdtcr;
-};
-
-#define DV_TIMER_TCR_ENAMODE_MASK		3
-
-#define DV_TIMER_TCR_ENAMODE12_SHIFT		6
-#define DV_TIMER_TCR_CLKSRC12_SHIFT		8
-#define DV_TIMER_TCR_READRSTMODE12_SHIFT	10
-#define DV_TIMER_TCR_CAPMODE12_SHIFT		11
-#define DV_TIMER_TCR_CAPVTMODE12_SHIFT		12
-#define DV_TIMER_TCR_ENAMODE34_SHIFT		22
-#define DV_TIMER_TCR_CLKSRC34_SHIFT		24
-#define DV_TIMER_TCR_READRSTMODE34_SHIFT	26
-#define DV_TIMER_TCR_CAPMODE34_SHIFT		27
-#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT		28
-
-#define DV_WDT_ENABLE_SYS_RESET		0x00020000
-#define DV_WDT_TRIGGER_SYS_RESET	0x00020002
-
-#ifdef CONFIG_HW_WATCHDOG
-void davinci_hw_watchdog_enable(void);
-void davinci_hw_watchdog_reset(void);
-#endif
-#endif /* _TIMER_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index db24dc0e89..2a17dfc6de 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -26,6 +26,10 @@ enum pll_src_bit {
 	EXYNOS_SRC_MPLL = 6,
 	EXYNOS_SRC_EPLL,
 	EXYNOS_SRC_VPLL,
+	EXYNOS542X_SRC_MPLL = 3,
+	EXYNOS542X_SRC_SPLL,
+	EXYNOS542X_SRC_EPLL = 6,
+	EXYNOS542X_SRC_RPLL,
 };
 
 unsigned long get_pll_clk(int pllreg);
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index da551e8839..b140c1fac2 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -30,11 +30,44 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
+
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
 
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE		0x06000000
 #define GICR_BASE		0x06100000
@@ -68,4 +101,9 @@
 #error SoC not defined
 #endif
 
+#ifdef CONFIG_LS2085A
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#endif
+
 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index ee1d6512d9..dd11ef79c8 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -15,6 +15,7 @@ struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
+	unsigned long freq_ddrbus2;
 	unsigned long freq_localbus;
 	unsigned long freq_qe;
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -60,6 +61,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK	0x1f
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT	10
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
 	u8	res_180[0x200-0x180];
 	u32	scratchrw[32];	/* Scratch Read/Write */
 	u8	res_280[0x300-0x280];
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
deleted file mode 100644
index d013b830ed..0000000000
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * K2E: Clock management APIs
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_K2E_H
-#define __ASM_ARCH_CLOCK_K2E_H
-
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	ddr3_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_clk,
-	xgmii_clk,
-	usb_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, ddr3_pll_clk)\
-	CLK(3, sys_clk0_clk)\
-	CLK(4, sys_clk0_1_clk)\
-	CLK(5, sys_clk0_2_clk)\
-	CLK(6, sys_clk0_3_clk)\
-	CLK(7, sys_clk0_4_clk)\
-	CLK(8, sys_clk0_6_clk)\
-	CLK(9, sys_clk0_8_clk)\
-	CLK(10, sys_clk0_12_clk)\
-	CLK(11, sys_clk0_24_clk)\
-	CLK(12, sys_clk1_clk)\
-	CLK(13, sys_clk1_3_clk)\
-	CLK(14, sys_clk1_4_clk)\
-	CLK(15, sys_clk1_6_clk)\
-	CLK(16, sys_clk1_12_clk)\
-	CLK(17, sys_clk2_clk)\
-	CLK(18, sys_clk3_clk)
-
-#define PLLSET_CMD_LIST	"<pa|ddr3>"
-
-#define KS2_CLK1_6	sys_clk0_6_clk
-
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	DDR3_PLL,
-};
-
-enum {
-	SPD800,
-	SPD850,
-	SPD1000,
-	SPD1250,
-	SPD1350,
-	SPD1400,
-	SPD1500,
-	SPD_RSV
-};
-
-#define CORE_PLL_800	{CORE_PLL, 16, 1, 2}
-#define CORE_PLL_850	{CORE_PLL, 17, 1, 2}
-#define CORE_PLL_1000	{CORE_PLL, 20, 1, 2}
-#define CORE_PLL_1200	{CORE_PLL, 24, 1, 2}
-#define PASS_PLL_1000	{PASS_PLL, 20, 1, 2}
-#define CORE_PLL_1250	{CORE_PLL, 25, 1, 2}
-#define CORE_PLL_1350	{CORE_PLL, 27, 1, 2}
-#define CORE_PLL_1400	{CORE_PLL, 28, 1, 2}
-#define CORE_PLL_1500	{CORE_PLL, 30, 1, 2}
-#define DDR3_PLL_200	{DDR3_PLL, 4,  1, 2}
-#define DDR3_PLL_400	{DDR3_PLL, 16, 1, 4}
-#define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
-#define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
deleted file mode 100644
index f28d5f0c4e..0000000000
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * K2HK: Clock management APIs
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_K2HK_H
-#define __ASM_ARCH_CLOCK_K2HK_H
-
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3a_clk,
-	ddr3b_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_srio_clk,
-	xgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3a_pll_clk)\
-	CLK(4, ddr3b_pll_clk)\
-	CLK(5, sys_clk0_clk)\
-	CLK(6, sys_clk0_1_clk)\
-	CLK(7, sys_clk0_2_clk)\
-	CLK(8, sys_clk0_3_clk)\
-	CLK(9, sys_clk0_4_clk)\
-	CLK(10, sys_clk0_6_clk)\
-	CLK(11, sys_clk0_8_clk)\
-	CLK(12, sys_clk0_12_clk)\
-	CLK(13, sys_clk0_24_clk)\
-	CLK(14, sys_clk1_clk)\
-	CLK(15, sys_clk1_3_clk)\
-	CLK(16, sys_clk1_4_clk)\
-	CLK(17, sys_clk1_6_clk)\
-	CLK(18, sys_clk1_12_clk)\
-	CLK(19, sys_clk2_clk)\
-	CLK(20, sys_clk3_clk)
-
-#define PLLSET_CMD_LIST		"<pa|arm|ddr3a|ddr3b>"
-
-#define KS2_CLK1_6 sys_clk0_6_clk
-
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	TETRIS_PLL,
-	DDR3A_PLL,
-	DDR3B_PLL,
-};
-
-enum {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD_RSV
-};
-
-#define CORE_PLL_799    {CORE_PLL,	13,	1,	2}
-#define CORE_PLL_983    {CORE_PLL,	16,	1,	2}
-#define CORE_PLL_999	{CORE_PLL,	122,	15,	1}
-#define CORE_PLL_1167   {CORE_PLL,	19,	1,	2}
-#define CORE_PLL_1228   {CORE_PLL,	20,	1,	2}
-#define CORE_PLL_1200	{CORE_PLL,	625,	32,	2}
-#define PASS_PLL_1228   {PASS_PLL,	20,	1,	2}
-#define PASS_PLL_983    {PASS_PLL,	16,	1,	2}
-#define PASS_PLL_1050   {PASS_PLL,	205,    12,	2}
-#define TETRIS_PLL_500  {TETRIS_PLL,	8,	1,	2}
-#define TETRIS_PLL_750  {TETRIS_PLL,	12,	1,	2}
-#define TETRIS_PLL_800	{TETRIS_PLL,	32,	5,	1}
-#define TETRIS_PLL_687  {TETRIS_PLL,	11,	1,	2}
-#define TETRIS_PLL_625  {TETRIS_PLL,	10,	1,	2}
-#define TETRIS_PLL_812  {TETRIS_PLL,	13,	1,	2}
-#define TETRIS_PLL_875  {TETRIS_PLL,	14,	1,	2}
-#define TETRIS_PLL_1000	{TETRIS_PLL,	40,	5,	1}
-#define TETRIS_PLL_1188 {TETRIS_PLL,	19,	2,	1}
-#define TETRIS_PLL_1200 {TETRIS_PLL,	48,	5,	1}
-#define TETRIS_PLL_1350	{TETRIS_PLL,	54,	5,	1}
-#define TETRIS_PLL_1375 {TETRIS_PLL,	22,	2,	1}
-#define TETRIS_PLL_1400 {TETRIS_PLL,	56,	5,	1}
-#define DDR3_PLL_200(x)	{DDR3##x##_PLL,	4,	1,	2}
-#define DDR3_PLL_400(x)	{DDR3##x##_PLL,	16,	1,	4}
-#define DDR3_PLL_800(x)	{DDR3##x##_PLL,	16,	1,	2}
-#define DDR3_PLL_333(x)	{DDR3##x##_PLL,	20,	1,	6}
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h
deleted file mode 100644
index bb9a5c4dcf..0000000000
--- a/arch/arm/include/asm/arch-keystone/clock-k2l.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * K2L: Clock management APIs
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_K2L_H
-#define __ASM_ARCH_CLOCK_K2L_H
-
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3_clk,
-	pcie_clk,
-	sgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3_pll_clk)\
-	CLK(4, sys_clk0_clk)\
-	CLK(5, sys_clk0_1_clk)\
-	CLK(6, sys_clk0_2_clk)\
-	CLK(7, sys_clk0_3_clk)\
-	CLK(8, sys_clk0_4_clk)\
-	CLK(9, sys_clk0_6_clk)\
-	CLK(10, sys_clk0_8_clk)\
-	CLK(11, sys_clk0_12_clk)\
-	CLK(12, sys_clk0_24_clk)\
-	CLK(13, sys_clk1_clk)\
-	CLK(14, sys_clk1_3_clk)\
-	CLK(15, sys_clk1_4_clk)\
-	CLK(16, sys_clk1_6_clk)\
-	CLK(17, sys_clk1_12_clk)\
-	CLK(18, sys_clk2_clk)\
-	CLK(19, sys_clk3_clk)\
-
-#define PLLSET_CMD_LIST	"<pa|arm|ddr3>"
-
-#define KS2_CLK1_6	sys_clk0_6_clk
-
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	TETRIS_PLL,
-	DDR3_PLL,
-};
-
-enum {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD_RSV
-};
-
-#define CORE_PLL_799	{CORE_PLL, 13, 1, 2}
-#define CORE_PLL_983	{CORE_PLL, 16, 1, 2}
-#define CORE_PLL_1000	{CORE_PLL, 114, 7, 2}
-#define CORE_PLL_1167	{CORE_PLL, 19, 1, 2}
-#define CORE_PLL_1198	{CORE_PLL, 39, 2, 2}
-#define CORE_PLL_1228	{CORE_PLL, 20, 1, 2}
-#define PASS_PLL_1228	{PASS_PLL, 20, 1, 2}
-#define PASS_PLL_983	{PASS_PLL, 16, 1, 2}
-#define PASS_PLL_1050	{PASS_PLL, 205, 12, 2}
-#define TETRIS_PLL_491	{TETRIS_PLL, 8, 1, 2}
-#define TETRIS_PLL_737	{TETRIS_PLL, 12, 1, 2}
-#define TETRIS_PLL_799	{TETRIS_PLL, 13, 1, 2}
-#define TETRIS_PLL_983	{TETRIS_PLL, 16, 1, 2}
-#define TETRIS_PLL_1000	{TETRIS_PLL, 114, 7, 2}
-#define TETRIS_PLL_1167	{TETRIS_PLL, 19, 1, 2}
-#define TETRIS_PLL_1198	{TETRIS_PLL, 39, 2, 2}
-#define TETRIS_PLL_1228	{TETRIS_PLL, 20, 1, 2}
-#define TETRIS_PLL_1352	{TETRIS_PLL, 22, 1, 2}
-#define TETRIS_PLL_1401	{TETRIS_PLL, 114, 5, 2}
-#define DDR3_PLL_200	{DDR3_PLL, 4, 1, 2}
-#define DDR3_PLL_400	{DDR3_PLL, 16, 1, 4}
-#define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
-#define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
deleted file mode 100644
index 9f6cfb265f..0000000000
--- a/arch/arm/include/asm/arch-keystone/clock.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * keystone2: common clock header file
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SOC_K2HK
-#include <asm/arch/clock-k2hk.h>
-#endif
-
-#ifdef CONFIG_SOC_K2E
-#include <asm/arch/clock-k2e.h>
-#endif
-
-#ifdef CONFIG_SOC_K2L
-#include <asm/arch/clock-k2l.h>
-#endif
-
-#define MAIN_PLL CORE_PLL
-
-#include <asm/types.h>
-
-#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
-#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
-#define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
-
-enum clk_e {
-	CLK_LIST(GENERATE_ENUM)
-};
-
-struct keystone_pll_regs {
-	u32 reg0;
-	u32 reg1;
-};
-
-/* PLL configuration data */
-struct pll_init_data {
-	int pll;
-	int pll_m;		/* PLL Multiplier */
-	int pll_d;		/* PLL divider */
-	int pll_od;		/* PLL output divider */
-};
-
-extern const struct keystone_pll_regs keystone_pll_regs[];
-extern int dev_speeds[];
-extern int arm_speeds[];
-
-void init_plls(int num_pll, struct pll_init_data *config);
-void init_pll(const struct pll_init_data *data);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-void pass_pll_pa_clk_enable(void);
-int get_max_dev_speed(void);
-int get_max_arm_speed(void);
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
deleted file mode 100644
index 85a046b89a..0000000000
--- a/arch/arm/include/asm/arch-keystone/clock_defs.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * keystone2: common pll clock definitions
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _CLOCK_DEFS_H_
-#define _CLOCK_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-#define BIT(x)			(1 << (x))
-
-/* PLL Control Registers */
-struct pllctl_regs {
-	u32	ctl;		/* 00 */
-	u32	ocsel;		/* 04 */
-	u32	secctl;		/* 08 */
-	u32	resv0;
-	u32	mult;		/* 10 */
-	u32	prediv;		/* 14 */
-	u32	div1;		/* 18 */
-	u32	div2;		/* 1c */
-	u32	div3;		/* 20 */
-	u32	oscdiv1;	/* 24 */
-	u32	resv1;		/* 28 */
-	u32	bpdiv;		/* 2c */
-	u32	wakeup;		/* 30 */
-	u32	resv2;
-	u32	cmd;		/* 38 */
-	u32	stat;		/* 3c */
-	u32	alnctl;		/* 40 */
-	u32	dchange;	/* 44 */
-	u32	cken;		/* 48 */
-	u32	ckstat;		/* 4c */
-	u32	systat;		/* 50 */
-	u32	ckctl;		/* 54 */
-	u32	resv3[2];
-	u32	div4;		/* 60 */
-	u32	div5;		/* 64 */
-	u32	div6;		/* 68 */
-	u32	div7;		/* 6c */
-	u32	div8;		/* 70 */
-	u32	div9;		/* 74 */
-	u32	div10;		/* 78 */
-	u32	div11;		/* 7c */
-	u32	div12;		/* 80 */
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
-	(struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
-};
-
-#define pllctl_reg(pll, reg)            (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg)       __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
-	pllctl_reg_write(pll, reg, \
-		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
-	pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
-	pllctl_reg_rmw(pll, reg, mask, 0)
-
-#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
-
-/* PLLCTL Bits */
-#define PLLCTL_BYPASS           BIT(23)
-#define PLL_PLLRST              BIT(14)
-#define PLLCTL_PAPLL            BIT(13)
-#define PLLCTL_CLKMODE          BIT(8)
-#define PLLCTL_PLLSELB          BIT(7)
-#define PLLCTL_ENSAT            BIT(6)
-#define PLLCTL_PLLENSRC         BIT(5)
-#define PLLCTL_PLLDIS           BIT(4)
-#define PLLCTL_PLLRST           BIT(3)
-#define PLLCTL_PLLPWRDN         BIT(1)
-#define PLLCTL_PLLEN            BIT(0)
-#define PLLSTAT_GO              BIT(0)
-
-#define MAIN_ENSAT_OFFSET       6
-
-#define PLLDIV_ENABLE           BIT(15)
-
-#define PLL_DIV_MASK            0x3f
-#define PLL_MULT_MASK           0x1fff
-#define PLL_MULT_SHIFT          6
-#define PLLM_MULT_HI_MASK       0x7f
-#define PLLM_MULT_HI_SHIFT      12
-#define PLLM_MULT_HI_SMASK      (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
-#define PLLM_MULT_LO_MASK       0x3f
-#define PLL_CLKOD_MASK          0xf
-#define PLL_CLKOD_SHIFT         19
-#define PLL_CLKOD_SMASK         (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
-#define PLL_BWADJ_LO_MASK       0xff
-#define PLL_BWADJ_LO_SHIFT      24
-#define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
-#define PLL_BWADJ_HI_MASK       0xf
-
-#define PLLM_RATIO_DIV1         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3         (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4         (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5         (PLLDIV_ENABLE | 0x17)
-
-#endif  /* _CLOCK_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h
deleted file mode 100644
index b044d6f18f..0000000000
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * DDR3
- *
- * (C) Copyright 2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _DDR3_H_
-#define _DDR3_H_
-
-#include <asm/arch/hardware.h>
-
-struct ddr3_phy_config {
-	unsigned int pllcr;
-	unsigned int pgcr1_mask;
-	unsigned int pgcr1_val;
-	unsigned int ptr0;
-	unsigned int ptr1;
-	unsigned int ptr2;
-	unsigned int ptr3;
-	unsigned int ptr4;
-	unsigned int dcr_mask;
-	unsigned int dcr_val;
-	unsigned int dtpr0;
-	unsigned int dtpr1;
-	unsigned int dtpr2;
-	unsigned int mr0;
-	unsigned int mr1;
-	unsigned int mr2;
-	unsigned int dtcr;
-	unsigned int pgcr2;
-	unsigned int zq0cr1;
-	unsigned int zq1cr1;
-	unsigned int zq2cr1;
-	unsigned int pir_v1;
-	unsigned int pir_v2;
-};
-
-struct ddr3_emif_config {
-	unsigned int sdcfg;
-	unsigned int sdtim1;
-	unsigned int sdtim2;
-	unsigned int sdtim3;
-	unsigned int sdtim4;
-	unsigned int zqcfg;
-	unsigned int sdrfc;
-};
-
-void ddr3_init(void);
-int ddr3_get_size(void);
-void ddr3_reset_ddrphy(void);
-void ddr3_init_ecc(u32 base);
-void ddr3_disable_ecc(u32 base);
-void ddr3_check_ecc_int(u32 base);
-int ddr3_ecc_support_rmw(u32 base);
-void ddr3_err_reset_workaround(void);
-void ddr3_enable_ecc(u32 base, int test);
-void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
-void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h
deleted file mode 100644
index df499957e5..0000000000
--- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * K2E: SoC definitions
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_K2E_H
-#define __ASM_ARCH_HARDWARE_K2E_H
-
-/* PA SS Registers */
-#define KS2_PASS_BASE			0x24000000
-
-/* Power and Sleep Controller (PSC) Domains */
-#define KS2_LPSC_MOD_RST		0
-#define KS2_LPSC_USB_1			1
-#define KS2_LPSC_USB			2
-#define KS2_LPSC_EMIF25_SPI		3
-#define KS2_LPSC_TSIP			4
-#define KS2_LPSC_DEBUGSS_TRC		5
-#define KS2_LPSC_TETB_TRC		6
-#define KS2_LPSC_PKTPROC		7
-#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
-#define KS2_LPSC_SGMII			8
-#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
-#define KS2_LPSC_CRYPTO			9
-#define KS2_LPSC_PCIE			10
-#define KS2_LPSC_VUSR0			12
-#define KS2_LPSC_CHIP_SRSS		13
-#define KS2_LPSC_MSMC			14
-#define KS2_LPSC_EMIF4F_DDR3		23
-#define KS2_LPSC_PCIE_1			27
-#define KS2_LPSC_XGE			50
-
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1		13
-
-/* Chip Interrupt Controller */
-#define KS2_CIC2_DDR3_ECC_IRQ_NUM	-1	/* not defined in K2E */
-#define KS2_CIC2_DDR3_ECC_CHAN_NUM	-1	/* not defined in K2E */
-
-/* SGMII SerDes */
-#define KS2_SGMII_SERDES2_BASE		0x02324000
-#define KS2_LANES_PER_SGMII_SERDES	4
-
-/* Number of DSP cores */
-#define KS2_NUM_DSPS			1
-
-/* NETCP pktdma */
-#define KS2_NETCP_PDMA_CTRL_BASE	0x24186000
-#define KS2_NETCP_PDMA_TX_BASE		0x24187000
-#define KS2_NETCP_PDMA_TX_CH_NUM	21
-#define KS2_NETCP_PDMA_RX_BASE		0x24188000
-#define KS2_NETCP_PDMA_RX_CH_NUM	91
-#define KS2_NETCP_PDMA_SCHED_BASE	0x24186100
-#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x24189000
-#define KS2_NETCP_PDMA_RX_FLOW_NUM	96
-#define KS2_NETCP_PDMA_TX_SND_QUEUE	896
-
-/* NETCP */
-#define KS2_NETCP_BASE			0x24000000
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
deleted file mode 100644
index 195c0d3003..0000000000
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * K2HK: SoC definitions
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_K2HK_H
-#define __ASM_ARCH_HARDWARE_K2HK_H
-
-#define KS2_ARM_PLL_EN			BIT(13)
-
-/* PA SS Registers */
-#define KS2_PASS_BASE			0x02000000
-
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
-/* Power and Sleep Controller (PSC) Domains */
-#define KS2_LPSC_MOD			0
-#define KS2_LPSC_DUMMY1			1
-#define KS2_LPSC_USB			2
-#define KS2_LPSC_EMIF25_SPI		3
-#define KS2_LPSC_TSIP			4
-#define KS2_LPSC_DEBUGSS_TRC		5
-#define KS2_LPSC_TETB_TRC		6
-#define KS2_LPSC_PKTPROC		7
-#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
-#define KS2_LPSC_SGMII			8
-#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
-#define KS2_LPSC_CRYPTO			9
-#define KS2_LPSC_PCIE			10
-#define KS2_LPSC_SRIO			11
-#define KS2_LPSC_VUSR0			12
-#define KS2_LPSC_CHIP_SRSS		13
-#define KS2_LPSC_MSMC			14
-#define KS2_LPSC_GEM_1			16
-#define KS2_LPSC_GEM_2			17
-#define KS2_LPSC_GEM_3			18
-#define KS2_LPSC_GEM_4			19
-#define KS2_LPSC_GEM_5			20
-#define KS2_LPSC_GEM_6			21
-#define KS2_LPSC_GEM_7			22
-#define KS2_LPSC_EMIF4F_DDR3A		23
-#define KS2_LPSC_EMIF4F_DDR3B		24
-#define KS2_LPSC_TAC			25
-#define KS2_LPSC_RAC			26
-#define KS2_LPSC_RAC_1			27
-#define KS2_LPSC_FFTC_A			28
-#define KS2_LPSC_FFTC_B			29
-#define KS2_LPSC_FFTC_C			30
-#define KS2_LPSC_FFTC_D			31
-#define KS2_LPSC_FFTC_E			32
-#define KS2_LPSC_FFTC_F			33
-#define KS2_LPSC_AI2			34
-#define KS2_LPSC_TCP3D_0		35
-#define KS2_LPSC_TCP3D_1		36
-#define KS2_LPSC_TCP3D_2		37
-#define KS2_LPSC_TCP3D_3		38
-#define KS2_LPSC_VCP2X4_A		39
-#define KS2_LPSC_CP2X4_B		40
-#define KS2_LPSC_VCP2X4_C		41
-#define KS2_LPSC_VCP2X4_D		42
-#define KS2_LPSC_VCP2X4_E		43
-#define KS2_LPSC_VCP2X4_F		44
-#define KS2_LPSC_VCP2X4_G		45
-#define KS2_LPSC_VCP2X4_H		46
-#define KS2_LPSC_BCP			47
-#define KS2_LPSC_DXB			48
-#define KS2_LPSC_VUSR1			49
-#define KS2_LPSC_XGE			50
-#define KS2_LPSC_ARM_SREFLEX		51
-
-/* DDR3B definitions */
-#define KS2_DDR3B_EMIF_CTRL_BASE	0x21020000
-#define KS2_DDR3B_EMIF_DATA_BASE	0x60000000
-#define KS2_DDR3B_DDRPHYC		0x02328000
-
-#define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3 /* DDR3 ECC system irq number */
-#define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D /* DDR3 ECC int mapped to CIC2
-						 channel 29 */
-
-/* SGMII SerDes */
-#define KS2_LANES_PER_SGMII_SERDES	4
-
-/* Number of DSP cores */
-#define KS2_NUM_DSPS			8
-
-/* NETCP pktdma */
-#define KS2_NETCP_PDMA_CTRL_BASE	0x02004000
-#define KS2_NETCP_PDMA_TX_BASE		0x02004400
-#define KS2_NETCP_PDMA_TX_CH_NUM	9
-#define KS2_NETCP_PDMA_RX_BASE		0x02004800
-#define KS2_NETCP_PDMA_RX_CH_NUM	26
-#define KS2_NETCP_PDMA_SCHED_BASE	0x02004c00
-#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x02005000
-#define KS2_NETCP_PDMA_RX_FLOW_NUM	32
-#define KS2_NETCP_PDMA_TX_SND_QUEUE	648
-
-/* NETCP */
-#define KS2_NETCP_BASE			0x02000000
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
deleted file mode 100644
index 4f1197ea92..0000000000
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * K2L: SoC definitions
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_K2L_H
-#define __ASM_ARCH_HARDWARE_K2L_H
-
-#define KS2_ARM_PLL_EN			BIT(13)
-
-/* PA SS Registers */
-#define KS2_PASS_BASE			0x26000000
-
-/* Power and Sleep Controller (PSC) Domains */
-#define KS2_LPSC_MOD			0
-#define KS2_LPSC_DFE_IQN_SYS		1
-#define KS2_LPSC_USB			2
-#define KS2_LPSC_EMIF25_SPI		3
-#define KS2_LPSC_TSIP                   4
-#define KS2_LPSC_DEBUGSS_TRC		5
-#define KS2_LPSC_TETB_TRC		6
-#define KS2_LPSC_PKTPROC		7
-#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
-#define KS2_LPSC_SGMII			8
-#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
-#define KS2_LPSC_CRYPTO			9
-#define KS2_LPSC_PCIE0			10
-#define KS2_LPSC_PCIE1			11
-#define KS2_LPSC_JESD_MISC		12
-#define KS2_LPSC_CHIP_SRSS		13
-#define KS2_LPSC_MSMC			14
-#define KS2_LPSC_GEM_1			16
-#define KS2_LPSC_GEM_2			17
-#define KS2_LPSC_GEM_3			18
-#define KS2_LPSC_EMIF4F_DDR3		23
-#define KS2_LPSC_TAC			25
-#define KS2_LPSC_RAC			26
-#define KS2_LPSC_DDUC4X_CFR2X_BB	27
-#define KS2_LPSC_FFTC_A			28
-#define KS2_LPSC_OSR			34
-#define KS2_LPSC_TCP3D_0		35
-#define KS2_LPSC_TCP3D_1		37
-#define KS2_LPSC_VCP2X4_A		39
-#define KS2_LPSC_VCP2X4_B		40
-#define KS2_LPSC_VCP2X4_C		41
-#define KS2_LPSC_VCP2X4_D		42
-#define KS2_LPSC_BCP			47
-#define KS2_LPSC_DPD4X			48
-#define KS2_LPSC_FFTC_B			49
-#define KS2_LPSC_IQN_AIL		50
-
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1		14
-
-/* Chip Interrupt Controller */
-#define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3
-#define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D
-
-/* OSR */
-#define KS2_OSR_DATA_BASE		0x70000000	/* OSR data base */
-#define KS2_OSR_CFG_BASE		0x02348c00	/* OSR config base */
-#define KS2_OSR_ECC_VEC			0x08		/* ECC Vector reg */
-#define KS2_OSR_ECC_CTRL		0x14		/* ECC control reg */
-
-/* OSR ECC Vector register */
-#define KS2_OSR_ECC_VEC_TRIG_RD		BIT(15)		/* trigger a read op */
-#define KS2_OSR_ECC_VEC_RD_DONE		BIT(24)		/* read complete */
-
-#define KS2_OSR_ECC_VEC_RAM_ID_SH	0		/* RAM ID shift */
-#define KS2_OSR_ECC_VEC_RD_ADDR_SH	16		/* read address shift */
-
-/* OSR ECC control register */
-#define KS2_OSR_ECC_CTRL_EN		BIT(0)		/* ECC enable bit */
-#define KS2_OSR_ECC_CTRL_CHK		BIT(1)		/* ECC check bit */
-#define KS2_OSR_ECC_CTRL_RMW		BIT(2)		/* ECC check bit */
-
-/* Number of OSR RAM banks */
-#define KS2_OSR_NUM_RAM_BANKS		4
-
-/* OSR memory size */
-#define KS2_OSR_SIZE			0x100000
-
-/* SGMII SerDes */
-#define KS2_SGMII_SERDES2_BASE		0x02320000
-#define KS2_LANES_PER_SGMII_SERDES	2
-
-/* Number of DSP cores */
-#define KS2_NUM_DSPS			4
-
-/* NETCP pktdma */
-#define KS2_NETCP_PDMA_CTRL_BASE	0x26186000
-#define KS2_NETCP_PDMA_TX_BASE		0x26187000
-#define KS2_NETCP_PDMA_TX_CH_NUM	21
-#define KS2_NETCP_PDMA_RX_BASE		0x26188000
-#define KS2_NETCP_PDMA_RX_CH_NUM	91
-#define KS2_NETCP_PDMA_SCHED_BASE	0x26186100
-#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x26189000
-#define KS2_NETCP_PDMA_RX_FLOW_NUM	96
-#define KS2_NETCP_PDMA_TX_SND_QUEUE	896
-
-/* NETCP */
-#define KS2_NETCP_BASE			0x26000000
-
-#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
deleted file mode 100644
index 16cbcee12b..0000000000
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Keystone2: Common SoC definitions, structures etc.
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <config.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-#include <asm/io.h>
-
-#define	REG(addr)        (*(volatile unsigned int *)(addr))
-#define REG_P(addr)      ((volatile unsigned int *)(addr))
-
-typedef volatile unsigned int   dv_reg;
-typedef volatile unsigned int   *dv_reg_p;
-
-#endif
-
-#define		BIT(x)	(1 << (x))
-
-#define KS2_DDRPHY_PIR_OFFSET           0x04
-#define KS2_DDRPHY_PGCR0_OFFSET         0x08
-#define KS2_DDRPHY_PGCR1_OFFSET         0x0C
-#define KS2_DDRPHY_PGSR0_OFFSET         0x10
-#define KS2_DDRPHY_PGSR1_OFFSET         0x14
-#define KS2_DDRPHY_PLLCR_OFFSET         0x18
-#define KS2_DDRPHY_PTR0_OFFSET          0x1C
-#define KS2_DDRPHY_PTR1_OFFSET          0x20
-#define KS2_DDRPHY_PTR2_OFFSET          0x24
-#define KS2_DDRPHY_PTR3_OFFSET          0x28
-#define KS2_DDRPHY_PTR4_OFFSET          0x2C
-#define KS2_DDRPHY_DCR_OFFSET           0x44
-
-#define KS2_DDRPHY_DTPR0_OFFSET         0x48
-#define KS2_DDRPHY_DTPR1_OFFSET         0x4C
-#define KS2_DDRPHY_DTPR2_OFFSET         0x50
-
-#define KS2_DDRPHY_MR0_OFFSET           0x54
-#define KS2_DDRPHY_MR1_OFFSET           0x58
-#define KS2_DDRPHY_MR2_OFFSET           0x5C
-#define KS2_DDRPHY_DTCR_OFFSET          0x68
-#define KS2_DDRPHY_PGCR2_OFFSET         0x8C
-
-#define KS2_DDRPHY_ZQ0CR1_OFFSET        0x184
-#define KS2_DDRPHY_ZQ1CR1_OFFSET        0x194
-#define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
-#define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
-
-#define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
-
-#define IODDRM_MASK                     0x00000180
-#define ZCKSEL_MASK                     0x01800000
-#define CL_MASK                         0x00000072
-#define WR_MASK                         0x00000E00
-#define BL_MASK                         0x00000003
-#define RRMODE_MASK                     0x00040000
-#define UDIMM_MASK                      0x20000000
-#define BYTEMASK_MASK                   0x0003FC00
-#define MPRDQ_MASK                      0x00000080
-#define PDQ_MASK                        0x00000070
-#define NOSRA_MASK                      0x08000000
-#define ECC_MASK                        0x00000001
-
-/* DDR3 definitions */
-#define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
-#define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
-#define KS2_DDR3A_DDRPHYC		0x02329000
-
-#define KS2_DDR3_MIDR_OFFSET            0x00
-#define KS2_DDR3_STATUS_OFFSET          0x04
-#define KS2_DDR3_SDCFG_OFFSET           0x08
-#define KS2_DDR3_SDRFC_OFFSET           0x10
-#define KS2_DDR3_SDTIM1_OFFSET          0x18
-#define KS2_DDR3_SDTIM2_OFFSET          0x1C
-#define KS2_DDR3_SDTIM3_OFFSET          0x20
-#define KS2_DDR3_SDTIM4_OFFSET          0x28
-#define KS2_DDR3_PMCTL_OFFSET           0x38
-#define KS2_DDR3_ZQCFG_OFFSET           0xC8
-
-#define KS2_DDR3_PLLCTRL_PHY_RESET	0x80000000
-
-/* DDR3 ECC */
-#define KS2_DDR3_ECC_INT_STATUS_OFFSET			0x0AC
-#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET		0x0B4
-#define KS2_DDR3_ECC_CTRL_OFFSET			0x110
-#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET			0x114
-#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET		0x130
-#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET	0x13C
-
-/* DDR3 ECC Interrupt Status register */
-#define KS2_DDR3_1B_ECC_ERR_SYS		BIT(5)
-#define KS2_DDR3_2B_ECC_ERR_SYS		BIT(4)
-#define KS2_DDR3_WR_ECC_ERR_SYS		BIT(3)
-
-/* DDR3 ECC Control register */
-#define KS2_DDR3_ECC_EN			BIT(31)
-#define KS2_DDR3_ECC_ADDR_RNG_PROT	BIT(30)
-#define KS2_DDR3_ECC_VERIFY_EN		BIT(29)
-#define KS2_DDR3_ECC_RMW_EN		BIT(28)
-#define KS2_DDR3_ECC_ADDR_RNG_1_EN	BIT(0)
-
-#define KS2_DDR3_ECC_ENABLE		(KS2_DDR3_ECC_EN | \
-					KS2_DDR3_ECC_ADDR_RNG_PROT | \
-					KS2_DDR3_ECC_VERIFY_EN)
-
-/* EDMA */
-#define KS2_EDMA0_BASE			0x02700000
-
-/* EDMA3 register offsets */
-#define KS2_EDMA_QCHMAP0		0x0200
-#define KS2_EDMA_IPR			0x1068
-#define KS2_EDMA_ICR			0x1070
-#define KS2_EDMA_QEECR			0x1088
-#define KS2_EDMA_QEESR			0x108c
-#define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
-
-/* NETCP pktdma */
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
-
-/* Chip Interrupt Controller */
-#define KS2_CIC2_BASE			0x02608000
-
-/* Chip Interrupt Controller register offsets */
-#define KS2_CIC_CTRL			0x04
-#define KS2_CIC_HOST_CTRL		0x0C
-#define KS2_CIC_GLOBAL_ENABLE		0x10
-#define KS2_CIC_SYS_ENABLE_IDX_SET	0x28
-#define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
-#define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
-
-#define KS2_UART0_BASE                	0x02530c00
-#define KS2_UART1_BASE                	0x02531000
-
-/* Boot Config */
-#define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
-#define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-#define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
-
-/* PSC */
-#define KS2_PSC_BASE			0x02350000
-#define KS2_LPSC_GEM_0			15
-#define KS2_LPSC_TETRIS			52
-#define KS2_TETRIS_PWR_DOMAIN		31
-
-/* Chip configuration unlock codes and registers */
-#define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KS2_KICK0_MAGIC			0x83e70b13
-#define KS2_KICK1_MAGIC			0x95a4f1e0
-
-/* PLL control registers */
-#define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
-#define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
-
-#define KS2_PLL_CNTRL_BASE		0x02310000
-#define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
-#define KS2_RSTCTRL_RSTYPE		(KS2_PLL_CNTRL_BASE + 0xe4)
-#define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_RSCFG		(KS2_PLL_CNTRL_BASE + 0xec)
-#define KS2_RSTCTRL_KEY			0x5a69
-#define KS2_RSTCTRL_MASK		0xffff0000
-#define KS2_RSTCTRL_SWRST		0xfffe0000
-#define KS2_RSTYPE_PLL_SOFT		BIT(13)
-
-/* SPI */
-#define KS2_SPI0_BASE			0x21000400
-#define KS2_SPI1_BASE			0x21000600
-#define KS2_SPI2_BASE			0x21000800
-#define KS2_SPI_BASE			KS2_SPI0_BASE
-
-/* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE       	0x21000a00
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
-
-/* Flag from ks2_debug options to check if DSPs need to stay ON */
-#define DBG_LEAVE_DSPS_ON		0x1
-
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE		0x0bc00000
-#define KS2_MSMC_DATA_BASE		0x0c000000
-#define KS2_MSMC_SEGMENT_TETRIS		8
-#define KS2_MSMC_SEGMENT_NETCP		9
-#define KS2_MSMC_SEGMENT_QM_PDSP	10
-#define KS2_MSMC_SEGMENT_PCIE0		11
-
-/* MSMC segment size shift bits */
-#define KS2_MSMC_SEG_SIZE_SHIFT		12
-#define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
-#define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
-					KS2_MSMC_SEG_SIZE_SHIFT)
-
-/* Device speed */
-#define KS2_REV1_DEVSPEED		(KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
-#define KS2_EFUSE_BOOTROM		(KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
-#define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
-/* Queue manager */
-#define KS2_QM_BASE_ADDRESS		0x23a80000
-#define KS2_QM_CONF_BASE		0x02a02000
-#define KS2_QM_DESC_SETUP_BASE		0x02a03000
-#define KS2_QM_STATUS_RAM_BASE		0x02a06000
-#define KS2_QM_INTD_CONF_BASE		0x02a0c000
-#define KS2_QM_PDSP1_CMD_BASE		0x02a20000
-#define KS2_QM_PDSP1_CTRL_BASE		0x02a0f000
-#define KS2_QM_PDSP1_IRAM_BASE		0x02a10000
-#define KS2_QM_MANAGER_QUEUES_BASE	0x02a80000
-#define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
-#define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
-#define KS2_QM_LINK_RAM_BASE		0x00100000
-#define KS2_QM_REGION_NUM		64
-#define KS2_QM_QPOOL_NUM		4000
-
-/* USB */
-#define KS2_USB_SS_BASE			0x02680000
-#define KS2_USB_HOST_XHCI_BASE		(KS2_USB_SS_BASE + 0x10000)
-#define KS2_DEV_USB_PHY_BASE		0x02620738
-#define KS2_USB_PHY_CFG_BASE		0x02630000
-
-#define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-/* SGMII SerDes */
-#define KS2_SGMII_SERDES_BASE		0x0232a000
-
-#ifdef CONFIG_SOC_K2HK
-#include <asm/arch/hardware-k2hk.h>
-#endif
-
-#ifdef CONFIG_SOC_K2E
-#include <asm/arch/hardware-k2e.h>
-#endif
-
-#ifdef CONFIG_SOC_K2L
-#include <asm/arch/hardware-k2l.h>
-#endif
-
-#ifndef __ASSEMBLY__
-static inline int cpu_is_k2hk(void)
-{
-	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
-
-	return (part_no == 0xb981) ? 1 : 0;
-}
-
-static inline int cpu_is_k2e(void)
-{
-	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
-
-	return (part_no == 0xb9a6) ? 1 : 0;
-}
-
-static inline int cpu_is_k2l(void)
-{
-	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
-
-	return (part_no == 0xb9a7) ? 1 : 0;
-}
-
-static inline int cpu_revision(void)
-{
-	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int rev	= (jtag_id >> 28) & 0xf;
-
-	return rev;
-}
-
-int cpu_to_bus(u32 *ptr, u32 length);
-void sdelay(unsigned long);
-
-#endif
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h
deleted file mode 100644
index d4256526cc..0000000000
--- a/arch/arm/include/asm/arch-keystone/i2c_defs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * keystone: i2c driver definitions
- *
- * (C) Copyright 2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#ifndef _I2C_DEFS_H_
-#define _I2C_DEFS_H_
-
-#define I2C0_BASE		0x02530000
-#define I2C1_BASE		0x02530400
-#define I2C2_BASE		0x02530800
-#define I2C_BASE		I2C0_BASE
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h
deleted file mode 100644
index 33a28764bc..0000000000
--- a/arch/arm/include/asm/arch-keystone/mon.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * K2HK: secure kernel command header file
- *
- * (C) Copyright 2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _MON_H_
-#define _MON_H_
-
-int mon_power_off(int core_id);
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h
deleted file mode 100644
index 083f5ba052..0000000000
--- a/arch/arm/include/asm/arch-keystone/msmc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * MSMC controller
- *
- * (C) Copyright 2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _MSMC_H_
-#define _MSMC_H_
-
-#include <asm/arch/hardware.h>
-
-enum mpax_seg_size {
-	MPAX_SEG_4K = 0x0b,
-	MPAX_SEG_8K,
-	MPAX_SEG_16K,
-	MPAX_SEG_32K,
-	MPAX_SEG_64K,
-	MPAX_SEG_128K,
-	MPAX_SEG_256K,
-	MPAX_SEG_512K,
-	MPAX_SEG_1M,
-	MPAX_SEG_2M,
-	MPAX_SEG_4M,
-	MPAX_SEG_8M,
-	MPAX_SEG_16M,
-	MPAX_SEG_32M,
-	MPAX_SEG_64M,
-	MPAX_SEG_128M,
-	MPAX_SEG_256M,
-	MPAX_SEG_512M,
-	MPAX_SEG_1G,
-	MPAX_SEG_2G,
-	MPAX_SEG_4G
-};
-
-void msmc_share_all_segments(int priv_id);
-void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
-void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
-void msmc_map_ses_segment(int priv_id, int ses_pair,
-			  u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
-
-#endif
diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h
deleted file mode 100644
index 70d22cf217..0000000000
--- a/arch/arm/include/asm/arch-keystone/psc_defs.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#ifndef _PSC_DEFS_H_
-#define _PSC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-/*
- * FILE PURPOSE: Local Power Sleep Controller definitions
- *
- * FILE NAME: psc_defs.h
- *
- * DESCRIPTION: Provides local definitions for the power saver controller
- *
- */
-
-/* Register offsets */
-#define PSC_REG_PTCMD           0x120
-#define PSC_REG_PSTAT	        0x128
-#define PSC_REG_PDSTAT(x)       (0x200 + (4 * (x)))
-#define PSC_REG_PDCTL(x)        (0x300 + (4 * (x)))
-#define PSC_REG_MDCFG(x)        (0x600 + (4 * (x)))
-#define PSC_REG_MDSTAT(x)       (0x800 + (4 * (x)))
-#define PSC_REG_MDCTL(x)        (0xa00 + (4 * (x)))
-
-#define BOOTBITMASK(x, y)     ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
-				  (u32)1)) << ((u32)y)))
-
-#define BOOT_READ_BITFIELD(z, x, y)    (((u32)z) & BOOTBITMASK(x, y)) >> (y)
-#define BOOT_SET_BITFIELD(z, f, x, y)  (((u32)z) & ~BOOTBITMASK(x, y)) | \
-					 ((((u32)f) << (y)) & BOOTBITMASK(x, y))
-
-/* PDCTL */
-#define PSC_REG_PDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 0, 0)
-#define PSC_REG_PDCTL_SET_PDMODE(x, y)      BOOT_SET_BITFIELD((x), (y), 15, 12)
-
-/* PDSTAT */
-#define PSC_REG_PDSTAT_GET_STATE(x)         BOOT_READ_BITFIELD((x), 4, 0)
-
-/* MDCFG */
-#define PSC_REG_MDCFG_GET_PD(x)             BOOT_READ_BITFIELD((x), 20, 16)
-#define PSC_REG_MDCFG_GET_RESET_ISO(x)      BOOT_READ_BITFIELD((x), 14, 14)
-
-/* MDCTL */
-#define PSC_REG_MDCTL_SET_NEXT(x, y)        BOOT_SET_BITFIELD((x), (y), 4, 0)
-#define PSC_REG_MDCTL_SET_LRSTZ(x, y)       BOOT_SET_BITFIELD((x), (y), 8, 8)
-#define PSC_REG_MDCTL_GET_LRSTZ(x)          BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDCTL_SET_RESET_ISO(x, y)   BOOT_SET_BITFIELD((x), (y), \
-								  12, 12)
-
-/* MDSTAT */
-#define PSC_REG_MDSTAT_GET_STATUS(x)        BOOT_READ_BITFIELD((x), 5, 0)
-#define PSC_REG_MDSTAT_GET_LRSTZ(x)         BOOT_READ_BITFIELD((x), 8, 8)
-#define PSC_REG_MDSTAT_GET_LRSTDONE(x)      BOOT_READ_BITFIELD((x), 9, 9)
-
-/* PDCTL states */
-#define PSC_REG_VAL_PDCTL_NEXT_ON           1
-#define PSC_REG_VAL_PDCTL_NEXT_OFF          0
-
-#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP      0
-
-/* MDCTL states */
-#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE     0
-#define PSC_REG_VAL_MDCTL_NEXT_OFF              2
-#define PSC_REG_VAL_MDCTL_NEXT_ON               3
-
-/* MDSTAT states */
-#define PSC_REG_VAL_MDSTAT_STATE_ON             3
-#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
-#define PSC_REG_VAL_MDSTAT_STATE_OFF            2
-#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1       0x20
-#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2       0x21
-#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3       0x22
-
-/*
- * Timeout limit on checking PTSTAT. This is the number of times the
- * wait function will be called before giving up.
- */
-#define PSC_PTSTAT_TIMEOUT_LIMIT    100
-
-u32 psc_get_domain_num(u32 mod_num);
-int psc_enable_module(u32 mod_num);
-int psc_disable_module(u32 mod_num);
-int psc_disable_domain(u32 domain_num);
-
-#endif /* _PSC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h
deleted file mode 100644
index 3aab4e045f..0000000000
--- a/arch/arm/include/asm/arch-keystone/xhci-keystone.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * USB 3.0 DRD Controller
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#define USB3_PHY_REF_SSP_EN		BIT(29)
-#define USB3_PHY_OTG_VBUSVLDECTSEL	BIT(16)
-
-/* KEYSTONE2 XHCI PHY register structure */
-struct keystone_xhci_phy {
-	unsigned int phy_utmi;		/* ctl0 */
-	unsigned int phy_pipe;		/* ctl1 */
-	unsigned int phy_param_ctrl_1;	/* ctl2 */
-	unsigned int phy_param_ctrl_2;	/* ctl3 */
-	unsigned int phy_clock;		/* ctl4 */
-	unsigned int phy_pll;		/* ctl5 */
-};
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
deleted file mode 100644
index e77ac400d8..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Kirkwood platform
- */
-
-#ifndef _KW_CONFIG_H
-#define _KW_CONFIG_H
-
-#if defined (CONFIG_KW88F6281)
-#include <asm/arch/kw88f6281.h>
-#elif defined (CONFIG_KW88F6192)
-#include <asm/arch/kw88f6192.h>
-#else
-#error "SOC Name not defined"
-#endif /* CONFIG_KW88F6281 */
-
-#include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE	32
-				/* default Dcache Line length for kirkwood */
-#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
-#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
-#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
-#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
-
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
-#define CONFIG_NR_DRAM_BANKS_MAX	2
-
-#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
-#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
-#define MV_SATA_BASE		KW_SATA_BASE
-#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
-#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
-
-/*
- * NAND configuration
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_KIRKWOOD
-#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
-#define NAND_ALLOW_ERASE_ALL		1
-#endif
-
-/*
- * SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI			1
-#define CONFIG_KIRKWOOD_SPI		1
-#ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS		0
-#endif
-#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS		0
-#endif
-#ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ		50000000
-#endif
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_NETCONSOLE	/* include NetConsole support   */
-#define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * USB/EHCI
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MARVELL
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/*
- * IDE Support on SATA ports
- */
-#ifdef CONFIG_CMD_IDE
-#define __io
-#define CONFIG_CMD_EXT2
-#define CONFIG_MVSATA_IDE
-#define CONFIG_IDE_PREINIT
-#define CONFIG_MVSATA_IDE_USE_PORT1
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
-/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE		4
-/* Controller supports 48-bits LBA addressing */
-#define CONFIG_LBA48
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
-#define CONFIG_SYS_IDE_MAXBUS		2
-#define CONFIG_SYS_IDE_MAXDEVICE	2
-/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
-#endif /* CONFIG_CMD_IDE */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
-#endif
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
-#endif
-
-#endif /* _KW_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
deleted file mode 100644
index 926d347110..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _KWCPU_H
-#define _KWCPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
-			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
-
-#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
-
-#define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
-#define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
-#define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
-#define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
-#define SYSRST_CNT_1SEC_VAL		(25*1000000)
-#define KW_REG_MPP_OUT_DRV_REG		(KW_MPP_BASE + 0xE0)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum kwcpu_winen {
-	KWCPU_WIN_DISABLE,
-	KWCPU_WIN_ENABLE
-};
-
-enum kwcpu_target {
-	KWCPU_TARGET_RESERVED,
-	KWCPU_TARGET_MEMORY,
-	KWCPU_TARGET_1RESERVED,
-	KWCPU_TARGET_SASRAM,
-	KWCPU_TARGET_PCIE
-};
-
-enum kwcpu_attrib {
-	KWCPU_ATTR_SASRAM = 0x01,
-	KWCPU_ATTR_DRAM_CS0 = 0x0e,
-	KWCPU_ATTR_DRAM_CS1 = 0x0d,
-	KWCPU_ATTR_DRAM_CS2 = 0x0b,
-	KWCPU_ATTR_DRAM_CS3 = 0x07,
-	KWCPU_ATTR_NANDFLASH = 0x2f,
-	KWCPU_ATTR_SPIFLASH = 0x1e,
-	KWCPU_ATTR_BOOTROM = 0x1d,
-	KWCPU_ATTR_PCIE_IO = 0xe0,
-	KWCPU_ATTR_PCIE_MEM = 0xe8
-};
-
-/*
- * Default Device Address MAP BAR values
- */
-#define KW_DEFADR_PCI_MEM	0x90000000
-#define KW_DEFADR_PCI_IO	0xC0000000
-#define KW_DEFADR_PCI_IO_REMAP	0xC0000000
-#define KW_DEFADR_SASRAM	0xC8010000
-#define KW_DEFADR_NANDF		0xD8000000
-#define KW_DEFADR_SPIF		0xE8000000
-#define KW_DEFADR_BOOTROM	0xF8000000
-
-/*
- * read feroceon/sheeva core extra feature register
- * using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void)
-{
-	unsigned int val;
-	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
-			(val)::"cc");
-	return val;
-}
-
-/*
- * write feroceon/sheeva core extra feature register
- * using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
-			(val):"cc");
-	isb();
-}
-
-/*
- * MBus-L to Mbus Bridge Registers
- * Ref: Datasheet sec:A.3
- */
-struct kwwin_registers {
-	u32 ctrl;
-	u32 base;
-	u32 remap_lo;
-	u32 remap_hi;
-};
-
-/*
- * CPU control and status Registers
- * Ref: Datasheet sec:A.3.2
- */
-struct kwcpu_registers {
-	u32 config;	/*0x20100 */
-	u32 ctrl_stat;	/*0x20104 */
-	u32 rstoutn_mask; /* 0x20108 */
-	u32 sys_soft_rst; /* 0x2010C */
-	u32 ahb_mbus_cause_irq; /* 0x20110 */
-	u32 ahb_mbus_mask_irq; /* 0x20114 */
-	u32 pad1[2];
-	u32 ftdll_config; /* 0x20120 */
-	u32 pad2;
-	u32 l2_cfg;	/* 0x20128 */
-};
-
-/*
- * GPIO Registers
- * Ref: Datasheet sec:A.19
- */
-struct kwgpio_registers {
-	u32 dout;
-	u32 oe;
-	u32 blink_en;
-	u32 din_pol;
-	u32 din;
-	u32 irq_cause;
-	u32 irq_mask;
-	u32 irq_level;
-};
-
-/*
- * functions
- */
-unsigned char get_random_hex(void);
-unsigned int mvebu_sdram_bar(enum memory_bank bank);
-unsigned int mvebu_sdram_bs(enum memory_bank bank);
-void mvebu_sdram_size_adjust(enum memory_bank bank);
-int kw_config_adr_windows(void);
-void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
-		unsigned int gpp0_oe, unsigned int gpp1_oe);
-int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
-		unsigned int mpp16_23, unsigned int mpp24_31,
-		unsigned int mpp32_39, unsigned int mpp40_47,
-		unsigned int mpp48_55);
-unsigned int kw_winctrl_calcsize(unsigned int sizeval);
-#endif /* __ASSEMBLY__ */
-#endif /* _KWCPU_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h
deleted file mode 100644
index aa8c5da36d..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed kernel level irq handling. Took some macros from kernel to
- * allow build.
- *
- * Dieter Kiermaier dk-arm-linux@gmx.de
- */
-
-#ifndef __KIRKWOOD_GPIO_H
-#define __KIRKWOOD_GPIO_H
-
-/* got from kernel include/linux/bitops.h */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
-
-#define GPIO_MAX		50
-#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
-#define GPIO_OUT(pin)		(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)	(MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
-
-/*
- * Kirkwood-specific GPIO API
- */
-
-void kw_gpio_set_valid(unsigned pin, int mode);
-int kw_gpio_is_valid(unsigned pin, int mode);
-int kw_gpio_direction_input(unsigned pin);
-int kw_gpio_direction_output(unsigned pin, int value);
-int kw_gpio_get_value(unsigned pin);
-void kw_gpio_set_value(unsigned pin, int value);
-void kw_gpio_set_blink(unsigned pin, int blink);
-void kw_gpio_set_unused(unsigned pin);
-
-#define GPIO_INPUT_OK		(1 << 0)
-#define GPIO_OUTPUT_OK		(1 << 1)
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
deleted file mode 100644
index de220d57d4..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CONFIG_KW88F6192_H
-#define _CONFIG_KW88F6192_H
-
-/* SOC specific definations */
-#define KW88F6192_REGS_PHYS_BASE	0xf1000000
-#define KW_REGS_PHY_BASE		KW88F6192_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK	  166000000 /* 166MHz */
-
-#endif /* _CONFIG_KW88F6192_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
deleted file mode 100644
index ca88a300e0..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_KW88F6281_H
-#define _ASM_ARCH_KW88F6281_H
-
-/* SOC specific definitions */
-#define KW88F6281_REGS_PHYS_BASE	0xf1000000
-#define KW_REGS_PHY_BASE		KW88F6281_REGS_PHYS_BASE
-
-/* TCLK Core Clock definition */
-#ifndef CONFIG_SYS_TCLK
-#define CONFIG_SYS_TCLK	200000000 /* 200MHz */
-#endif
-
-#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h
deleted file mode 100644
index 7c8f6eba97..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/mpp.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
- *
- * Copyright 2009: Marvell Technology Group Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __KIRKWOOD_MPP_H
-#define __KIRKWOOD_MPP_H
-
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
-	/* MPP number */		((_num) & 0xff) | \
-	/* MPP select value */		(((_sel) & 0xf) << 8) | \
-	/* may be input signal */	((!!(_in)) << 12) | \
-	/* may be output signal */	((!!(_out)) << 13) | \
-	/* available on F6180 */	((!!(_F6180)) << 14) | \
-	/* available on F6190 */	((!!(_F6190)) << 15) | \
-	/* available on F6192 */	((!!(_F6192)) << 16) | \
-	/* available on F6281 */	((!!(_F6281)) << 17))
-
-#define MPP_NUM(x)	((x) & 0xff)
-#define MPP_SEL(x)	(((x) >> 8) & 0xf)
-
-				/*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI	MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO	MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0	DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO	MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI	MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK	MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12		MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO		MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI	MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO	MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO	MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI	MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK	MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
-
-#define MPP_MAX			49
-
-void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
-
-#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h
deleted file mode 100644
index 58ed71b186..0000000000
--- a/arch/arm/include/asm/arch-kirkwood/soc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for the Marvell's Feroceon CPU core.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_KIRKWOOD_H
-#define _ASM_ARCH_KIRKWOOD_H
-
-#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
-
-/* SOC specific definations */
-#define INTREG_BASE			0xd0000000
-#define KW_REGISTER(x)			(KW_REGS_PHY_BASE + x)
-#define KW_OFFSET_REG			(INTREG_BASE + 0x20080)
-
-/* undocumented registers */
-#define KW_REG_UNDOC_0x1470		(KW_REGISTER(0x1470))
-#define KW_REG_UNDOC_0x1478		(KW_REGISTER(0x1478))
-
-#define MVEBU_SDRAM_BASE		(KW_REGISTER(0x1500))
-#define KW_TWSI_BASE			(KW_REGISTER(0x11000))
-#define KW_UART0_BASE			(KW_REGISTER(0x12000))
-#define KW_UART1_BASE			(KW_REGISTER(0x12100))
-#define KW_MPP_BASE			(KW_REGISTER(0x10000))
-#define MVEBU_GPIO0_BASE			(KW_REGISTER(0x10100))
-#define MVEBU_GPIO1_BASE			(KW_REGISTER(0x10140))
-#define KW_RTC_BASE			(KW_REGISTER(0x10300))
-#define KW_NANDF_BASE			(KW_REGISTER(0x10418))
-#define MVEBU_SPI_BASE			(KW_REGISTER(0x10600))
-#define KW_CPU_WIN_BASE			(KW_REGISTER(0x20000))
-#define KW_CPU_REG_BASE			(KW_REGISTER(0x20100))
-#define MVEBU_TIMER_BASE			(KW_REGISTER(0x20300))
-#define KW_REG_PCIE_BASE		(KW_REGISTER(0x40000))
-#define KW_USB20_BASE			(KW_REGISTER(0x50000))
-#define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
-#define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
-#define KW_SATA_BASE			(KW_REGISTER(0x80000))
-#define KW_SDIO_BASE			(KW_REGISTER(0x90000))
-
-/* Kirkwood Sata controller has two ports */
-#define KW_SATA_PORT0_OFFSET		0x2000
-#define KW_SATA_PORT1_OFFSET		0x4000
-
-/* Kirkwood GbE controller has two ports */
-#define MAX_MVGBE_DEVS	2
-#define MVGBE0_BASE	KW_EGIGA0_BASE
-#define MVGBE1_BASE	KW_EGIGA1_BASE
-
-/* Kirkwood USB Host controller */
-#define MVUSB0_BASE			KW_USB20_BASE
-#define MVUSB0_CPU_ATTR_DRAM_CS0	KWCPU_ATTR_DRAM_CS0
-#define MVUSB0_CPU_ATTR_DRAM_CS1	KWCPU_ATTR_DRAM_CS1
-#define MVUSB0_CPU_ATTR_DRAM_CS2	KWCPU_ATTR_DRAM_CS2
-#define MVUSB0_CPU_ATTR_DRAM_CS3	KWCPU_ATTR_DRAM_CS3
-
-/* Kirkwood CPU memory windows */
-#define MVCPU_WIN_CTRL_DATA	KWCPU_WIN_CTRL_DATA
-#define MVCPU_WIN_ENABLE	KWCPU_WIN_ENABLE
-#define MVCPU_WIN_DISABLE	KWCPU_WIN_DISABLE
-
-#if defined (CONFIG_KW88F6281)
-#include <asm/arch/kw88f6281.h>
-#elif defined (CONFIG_KW88F6192)
-#include <asm/arch/kw88f6192.h>
-#else
-#error "SOC Name not defined"
-#endif /* CONFIG_KW88F6281 */
-#endif /* CONFIG_FEROCEON_88FR131 */
-#endif /* _ASM_ARCH_KIRKWOOD_H */
diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h
deleted file mode 100644
index 02f6049263..0000000000
--- a/arch/arm/include/asm/arch-ks8695/platform.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __address_h
-#define __address_h			1
-
-#define KS8695_SDRAM_START	    0x00000000
-#define KS8695_SDRAM_SIZE	    0x01000000
-#define KS8695_MEM_SIZE		    KS8695_SDRAM_SIZE
-#define KS8695_MEM_START	    KS8695_SDRAM_START
-
-#define KS8695_PCMCIA_IO_BASE	    0x03800000
-#define KS8695_PCMCIA_IO_SIZE	    0x00040000
-
-#define KS8695_IO_BASE		    0x03FF0000
-#define KS8695_IO_SIZE		    0x00010000
-
-#define KS8695_SYSTEN_CONFIG	    0x00
-#define KS8695_SYSTEN_BUS_CLOCK	    0x04
-
-#define KS8695_FLASH_START	    0x02800000
-#define KS8695_FLASH_SIZE	    0x00400000
-
-/*i/o control registers offset difinitions*/
-#define KS8695_IO_CTRL0		    0x4000
-#define KS8695_IO_CTRL1		    0x4004
-#define KS8695_IO_CTRL2		    0x4008
-#define KS8695_IO_CTRL3		    0x400C
-
-/*memory control registers offset difinitions*/
-#define KS8695_MEM_CTRL0	    0x4010
-#define KS8695_MEM_CTRL1	    0x4014
-#define KS8695_MEM_CTRL2	    0x4018
-#define KS8695_MEM_CTRL3	    0x401C
-#define KS8695_MEM_GENERAL	    0x4020
-#define KS8695_SDRAM_CTRL0	    0x4030
-#define KS8695_SDRAM_CTRL1	    0x4034
-#define KS8695_SDRAM_GENERAL	    0x4038
-#define KS8695_SDRAM_BUFFER	    0x403C
-#define KS8695_SDRAM_REFRESH	    0x4040
-
-/*WAN control registers offset difinitions*/
-#define KS8695_WAN_DMA_TX	    0x6000
-#define KS8695_WAN_DMA_RX	    0x6004
-#define KS8695_WAN_DMA_TX_START	    0x6008
-#define KS8695_WAN_DMA_RX_START	    0x600C
-#define KS8695_WAN_TX_LIST	    0x6010
-#define KS8695_WAN_RX_LIST	    0x6014
-#define KS8695_WAN_MAC_LOW	    0x6018
-#define KS8695_WAN_MAC_HIGH	    0x601C
-#define KS8695_WAN_MAC_ELOW	    0x6080
-#define KS8695_WAN_MAC_EHIGH	    0x6084
-
-/*LAN control registers offset difinitions*/
-#define KS8695_LAN_DMA_TX	    0x8000
-#define KS8695_LAN_DMA_RX	    0x8004
-#define KS8695_LAN_DMA_TX_START	    0x8008
-#define KS8695_LAN_DMA_RX_START	    0x800C
-#define KS8695_LAN_TX_LIST	    0x8010
-#define KS8695_LAN_RX_LIST	    0x8014
-#define KS8695_LAN_MAC_LOW	    0x8018
-#define KS8695_LAN_MAC_HIGH	    0x801C
-#define KS8695_LAN_MAC_ELOW	    0X8080
-#define KS8695_LAN_MAC_EHIGH	    0X8084
-
-/*HPNA control registers offset difinitions*/
-#define KS8695_HPNA_DMA_TX	    0xA000
-#define KS8695_HPNA_DMA_RX	    0xA004
-#define KS8695_HPNA_DMA_TX_START    0xA008
-#define KS8695_HPNA_DMA_RX_START    0xA00C
-#define KS8695_HPNA_TX_LIST	    0xA010
-#define KS8695_HPNA_RX_LIST	    0xA014
-#define KS8695_HPNA_MAC_LOW	    0xA018
-#define KS8695_HPNA_MAC_HIGH	    0xA01C
-#define KS8695_HPNA_MAC_ELOW	    0xA080
-#define KS8695_HPNA_MAC_EHIGH	    0xA084
-
-/*UART control registers offset difinitions*/
-#define KS8695_UART_RX_BUFFER	    0xE000
-#define KS8695_UART_TX_HOLDING	    0xE004
-
-#define KS8695_UART_FIFO_CTRL	    0xE008
-#define KS8695_UART_FIFO_TRIG01	    0x00
-#define KS8695_UART_FIFO_TRIG04	    0x80
-#define KS8695_UART_FIFO_TXRST	    0x03
-#define KS8695_UART_FIFO_RXRST	    0x02
-#define KS8695_UART_FIFO_FEN	    0x01
-
-#define KS8695_UART_LINE_CTRL	    0xE00C
-#define KS8695_UART_LINEC_BRK	    0x40
-#define KS8695_UART_LINEC_EPS	    0x10
-#define KS8695_UART_LINEC_PEN	    0x08
-#define KS8695_UART_LINEC_STP2	    0x04
-#define KS8695_UART_LINEC_WLEN8	    0x03
-#define KS8695_UART_LINEC_WLEN7	    0x02
-#define KS8695_UART_LINEC_WLEN6	    0x01
-#define KS8695_UART_LINEC_WLEN5	    0x00
-
-#define KS8695_UART_MODEM_CTRL	    0xE010
-#define KS8695_UART_MODEMC_RTS	    0x02
-#define KS8695_UART_MODEMC_DTR	    0x01
-
-#define KS8695_UART_LINE_STATUS	    0xE014
-#define KS8695_UART_LINES_TXFE	    0x20
-#define KS8695_UART_LINES_BE	    0x10
-#define KS8695_UART_LINES_FE	    0x08
-#define KS8695_UART_LINES_PE	    0x04
-#define KS8695_UART_LINES_OE	    0x02
-#define KS8695_UART_LINES_RXFE	    0x01
-#define KS8695_UART_LINES_ANY	    (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
-
-#define KS8695_UART_MODEM_STATUS    0xE018
-#define KS8695_UART_MODEM_DCD	    0x80
-#define KS8695_UART_MODEM_DSR	    0x20
-#define KS8695_UART_MODEM_CTS	    0x10
-#define KS8695_UART_MODEM_DDCD	    0x08
-#define KS8695_UART_MODEM_DDSR	    0x02
-#define KS8695_UART_MODEM_DCTS	    0x01
-#define UART8695_MODEM_ANY	    0xFF
-
-#define KS8695_UART_DIVISOR	    0xE01C
-#define KS8695_UART_STATUS	    0xE020
-
-/*Interrupt controlller registers offset difinitions*/
-#define KS8695_INT_CONTL	    0xE200
-#define KS8695_INT_ENABLE	    0xE204
-#define KS8695_INT_ENABLE_MODEM	    0x0800
-#define KS8695_INT_ENABLE_ERR	    0x0400
-#define KS8695_INT_ENABLE_RX	    0x0200
-#define KS8695_INT_ENABLE_TX	    0x0100
-
-#define KS8695_INT_STATUS	    0xE208
-#define KS8695_INT_WAN_PRIORITY	    0xE20C
-#define KS8695_INT_HPNA_PRIORITY    0xE210
-#define KS8695_INT_LAN_PRIORITY	    0xE214
-#define KS8695_INT_TIMER_PRIORITY   0xE218
-#define KS8695_INT_UART_PRIORITY    0xE21C
-#define KS8695_INT_EXT_PRIORITY	    0xE220
-#define KS8695_INT_CHAN_PRIORITY    0xE224
-#define KS8695_INT_BUSERROR_PRO	    0xE228
-#define KS8695_INT_MASK_STATUS	    0xE22C
-#define KS8695_FIQ_PEND_PRIORITY    0xE230
-#define KS8695_IRQ_PEND_PRIORITY    0xE234
-
-/*timer registers offset difinitions*/
-#define KS8695_TIMER_CTRL	    0xE400
-#define KS8695_TIMER1		    0xE404
-#define KS8695_TIMER0		    0xE408
-#define KS8695_TIMER1_PCOUNT	    0xE40C
-#define KS8695_TIMER0_PCOUNT	    0xE410
-
-/*GPIO registers offset difinitions*/
-#define KS8695_GPIO_MODE	    0xE600
-#define KS8695_GPIO_CTRL	    0xE604
-#define KS8695_GPIO_DATA	    0xE608
-
-/*SWITCH registers offset difinitions*/
-#define KS8695_SWITCH_CTRL0	    0xE800
-#define KS8695_SWITCH_CTRL1	    0xE804
-#define KS8695_SWITCH_PORT1	    0xE808
-#define KS8695_SWITCH_PORT2	    0xE80C
-#define KS8695_SWITCH_PORT3	    0xE810
-#define KS8695_SWITCH_PORT4	    0xE814
-#define KS8695_SWITCH_PORT5	    0xE818
-#define KS8695_SWITCH_AUTO0	    0xE81C
-#define KS8695_SWITCH_AUTO1	    0xE820
-#define KS8695_SWITCH_LUE_CTRL	    0xE824
-#define KS8695_SWITCH_LUE_HIGH	    0xE828
-#define KS8695_SWITCH_LUE_LOW	    0xE82C
-#define KS8695_SWITCH_ADVANCED	    0xE830
-
-#define KS8695_SWITCH_LPPM12	    0xE874
-#define KS8695_SWITCH_LPPM34	    0xE878
-
-/*host communication registers difinitions*/
-#define KS8695_DSCP_HIGH	    0xE834
-#define KS8695_DSCP_LOW		    0xE838
-#define KS8695_SWITCH_MAC_HIGH	    0xE83C
-#define KS8695_SWITCH_MAC_LOW	    0xE840
-
-/*miscellaneours registers difinitions*/
-#define KS8695_MANAGE_COUNTER	    0xE844
-#define KS8695_MANAGE_DATA	    0xE848
-#define KS8695_LAN12_POWERMAGR	    0xE84C
-#define KS8695_LAN34_POWERMAGR	    0xE850
-
-#define KS8695_DEVICE_ID	    0xEA00
-#define KS8695_REVISION_ID	    0xEA04
-
-#define KS8695_MISC_CONTROL	    0xEA08
-#define KS8695_WAN_CONTROL	    0xEA0C
-#define KS8695_WAN_POWERMAGR	    0xEA10
-#define KS8695_WAN_PHY_CONTROL	    0xEA14
-#define KS8695_WAN_PHY_STATUS	    0xEA18
-
-/* bus clock definitions*/
-#define KS8695_BUS_CLOCK_125MHZ	    0x0
-#define KS8695_BUS_CLOCK_100MHZ	    0x1
-#define KS8695_BUS_CLOCK_62MHZ	    0x2
-#define KS8695_BUS_CLOCK_50MHZ	    0x3
-#define KS8695_BUS_CLOCK_41MHZ	    0x4
-#define KS8695_BUS_CLOCK_33MHZ	    0x5
-#define KS8695_BUS_CLOCK_31MHZ	    0x6
-#define KS8695_BUS_CLOCK_25MHZ	    0x7
-
-/* -------------------------------------------------------------------------------
- *  definations for IRQ
- * -------------------------------------------------------------------------------*/
-
-#define KS8695_INT_EXT_INT0		       2
-#define KS8695_INT_EXT_INT1		       3
-#define KS8695_INT_EXT_INT2		       4
-#define KS8695_INT_EXT_INT3		       5
-#define KS8695_INT_TIMERINT0		       6
-#define KS8695_INT_TIMERINT1		       7
-#define KS8695_INT_UART_TX		       8
-#define KS8695_INT_UART_RX		       9
-#define KS8695_INT_UART_LINE_ERR	       10
-#define KS8695_INT_UART_MODEMS		       11
-#define KS8695_INT_LAN_STOP_RX		       12
-#define KS8695_INT_LAN_STOP_TX		       13
-#define KS8695_INT_LAN_BUF_RX_STATUS	       14
-#define KS8695_INT_LAN_BUF_TX_STATUS	       15
-#define KS8695_INT_LAN_RX_STATUS	       16
-#define KS8695_INT_LAN_TX_STATUS	       17
-#define KS8695_INT_HPAN_STOP_RX		       18
-#define KS8695_INT_HPNA_STOP_TX		       19
-#define KS8695_INT_HPNA_BUF_RX_STATUS	       20
-#define KS8695_INT_HPNA_BUF_TX_STATUS	       21
-#define KS8695_INT_HPNA_RX_STATUS	       22
-#define KS8695_INT_HPNA_TX_STATUS	       23
-#define KS8695_INT_BUS_ERROR		       24
-#define KS8695_INT_WAN_STOP_RX		       25
-#define KS8695_INT_WAN_STOP_TX		       26
-#define KS8695_INT_WAN_BUF_RX_STATUS	       27
-#define KS8695_INT_WAN_BUF_TX_STATUS	       28
-#define KS8695_INT_WAN_RX_STATUS	       29
-#define KS8695_INT_WAN_TX_STATUS	       30
-
-#define KS8695_INT_UART			       KS8695_INT_UART_TX
-
-/* -------------------------------------------------------------------------------
- *  Interrupt bit positions
- *
- * -------------------------------------------------------------------------------
- */
-
-#define KS8695_INTMASK_EXT_INT0		       ( 1 << KS8695_INT_EXT_INT0 )
-#define KS8695_INTMASK_EXT_INT1		       ( 1 << KS8695_INT_EXT_INT1 )
-#define KS8695_INTMASK_EXT_INT2		       ( 1 << KS8695_INT_EXT_INT2 )
-#define KS8695_INTMASK_EXT_INT3		       ( 1 << KS8695_INT_EXT_INT3 )
-#define KS8695_INTMASK_TIMERINT0	       ( 1 << KS8695_INT_TIMERINT0 )
-#define KS8695_INTMASK_TIMERINT1	       ( 1 << KS8695_INT_TIMERINT1 )
-#define KS8695_INTMASK_UART_TX		       ( 1 << KS8695_INT_UART_TX  )
-#define KS8695_INTMASK_UART_RX		       ( 1 << KS8695_INT_UART_RX  )
-#define KS8695_INTMASK_UART_LINE_ERR	       ( 1 << KS8695_INT_UART_LINE_ERR )
-#define KS8695_INTMASK_UART_MODEMS	       ( 1 << KS8695_INT_UART_MODEMS )
-#define KS8695_INTMASK_LAN_STOP_RX	       ( 1 << KS8695_INT_LAN_STOP_RX )
-#define KS8695_INTMASK_LAN_STOP_TX	       ( 1 << KS8695_INT_LAN_STOP_TX )
-#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_LAN_RX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_LAN_TX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
-#define KS8695_INTMASK_HPAN_STOP_RX	       ( 1 << KS8695_INT_HPAN_STOP_RX )
-#define KS8695_INTMASK_HPNA_STOP_TX	       ( 1 << KS8695_INT_HPNA_STOP_TX )
-#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
-#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
-#define KS8695_INTMASK_HPNA_RX_STATUS	       ( 1 << KS8695_INT_HPNA_RX_STATUS )
-#define KS8695_INTMASK_HPNA_TX_STATUS	       ( 1 << KS8695_INT_HPNA_TX_STATUS )
-#define KS8695_INTMASK_BUS_ERROR	       ( 1 << KS8695_INT_BUS_ERROR )
-#define KS8695_INTMASK_WAN_STOP_RX	       ( 1 << KS8695_INT_WAN_STOP_RX )
-#define KS8695_INTMASK_WAN_STOP_TX	       ( 1 << KS8695_INT_WAN_STOP_TX )
-#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
-#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
-#define KS8695_INTMASK_WAN_RX_STATUS	       ( 1 << KS8695_INT_WAN_RX_STATUS )
-#define KS8695_INTMASK_WAN_TX_STATUS	       ( 1 << KS8695_INT_WAN_TX_STATUS )
-
-#define KS8695_SC_VALID_INT		       0xFFFFFFFF
-#define MAXIRQNUM			       31
-
-/*
- *  Timer definitions
- *
- *  Use timer 1 & 2
- *  (both run at 25MHz).
- *
- */
-#define TICKS_PER_uSEC			25
-#define mSEC_1				1000
-#define mSEC_10				(mSEC_1 * 10)
-
-#endif
-
-/*	END */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426bc1b..564441cbfa 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -1,7 +1,7 @@
 /*
  * Common definitions for LPC32XX board configurations
  *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,6 +9,8 @@
 #ifndef _LPC32XX_CONFIG_H
 #define _LPC32XX_CONFIG_H
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* Basic CPU architecture */
 #define CONFIG_ARCH_CPU_INIT
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 791551841c..3b6a1696d8 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -36,6 +36,7 @@
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
 #define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
@@ -61,6 +62,20 @@
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 
+#define CONFIG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
+#define CONFIG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
+#define CONFIG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
+#define CONFIG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
+/*
+ * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
+ * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
+ */
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		(CONFIG_SYS_PCIE1_PHYS_BASE + \
+						 CONFIG_SYS_PCIE1_VIRT_ADDR)
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
+						 CONFIG_SYS_PCIE2_VIRT_ADDR)
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f70d568d46..3a64afce46 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -37,6 +37,43 @@
 
 #define DCFG_DCSR_PORCR1		0
 
+/*
+ * Define default values for some CCSR macros to make header files cleaner
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
@@ -133,8 +170,7 @@ struct ccsr_scfg {
 	u32 pex1rdmmsgrqsr;
 	u32 pex2rdmmsgrqsr;
 	u32 spimsiclrcr;
-	u32 pex1mscportsr;
-	u32 pex2mscportsr;
+	u32 pexmscportsr[2];
 	u32 pex2pmwrcr;
 	u32 resv5[24];
 	u32 mac1_streamid;
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index abd70fc706..fa571b3a38 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -7,11 +7,68 @@
 #ifndef __FSL_LS102XA_STREAM_ID_H_
 #define __FSL_LS102XA_STREAM_ID_H_
 
+#include <fsl_sec.h>
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA }, .num_ids = 1, \
+	  .reg_offset = off + CONFIG_SYS_IMMR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA, idB }, .num_ids = 2, \
+	  .reg_offset = off + CONFIG_SYS_IMMR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
+		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+struct liodn_id_table {
+	const char *compat;
+	u32 id[2];
+	u8 num_ids;
+	phys_addr_t compat_offset;
+	unsigned long reg_offset;
+};
+
 struct smmu_stream_id {
 	uint16_t offset;
 	uint16_t stream_id;
 	char dev_name[32];
 };
 
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
 void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
 #endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
deleted file mode 100644
index 42a52bc36c..0000000000
--- a/arch/arm/include/asm/arch-mb86r0x/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <linux/sizes.h>
-#include <asm/arch/mb86r0x.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
deleted file mode 100644
index 7fec9715b1..0000000000
--- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * (C) Copyright 2007
- *
- * mb86r0x definitions
- *
- * Author : Carsten Schneider, mycable GmbH
- *          <cs@mycable.de>
- *
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef MB86R0X_H
-#define MB86R0X_H
-
-#ifndef __ASSEMBLY__
-
-/* GPIO registers */
-struct mb86r0x_gpio {
-	uint32_t gpdr0;
-	uint32_t gpdr1;
-	uint32_t gpdr2;
-	uint32_t res;
-	uint32_t gpddr0;
-	uint32_t gpddr1;
-	uint32_t gpddr2;
-};
-
-/* PWM registers */
-struct mb86r0x_pwm {
-	uint32_t bcr;
-	uint32_t tpr;
-	uint32_t pr;
-	uint32_t dr;
-	uint32_t cr;
-	uint32_t sr;
-	uint32_t ccr;
-	uint32_t ir;
-};
-
-/* The mb86r0x chip control (CCNT) register set. */
-struct mb86r0x_ccnt {
-	uint32_t ccid;
-	uint32_t csrst;
-	uint32_t pad0[2];
-	uint32_t cist;
-	uint32_t cistm;
-	uint32_t cgpio_ist;
-	uint32_t cgpio_istm;
-	uint32_t cgpio_ip;
-	uint32_t cgpio_im;
-	uint32_t caxi_bw;
-	uint32_t caxi_ps;
-	uint32_t cmux_md;
-	uint32_t cex_pin_st;
-	uint32_t cmlb;
-	uint32_t pad1[1];
-	uint32_t cusb;
-	uint32_t pad2[41];
-	uint32_t cbsc;
-	uint32_t cdcrc;
-	uint32_t cmsr0;
-	uint32_t cmsr1;
-	uint32_t pad3[2];
-};
-
-/* The mb86r0x clock reset generator */
-struct mb86r0x_crg {
-	uint32_t crpr;
-	uint32_t pad0;
-	uint32_t crwr;
-	uint32_t crsr;
-	uint32_t crda;
-	uint32_t crdb;
-	uint32_t crha;
-	uint32_t crpa;
-	uint32_t crpb;
-	uint32_t crhb;
-	uint32_t cram;
-};
-
-/* The mb86r0x timer */
-struct mb86r0x_timer {
-	uint32_t load;
-	uint32_t value;
-	uint32_t control;
-	uint32_t intclr;
-	uint32_t ris;
-	uint32_t mis;
-	uint32_t bgload;
-};
-
-/* mb86r0x gdc display controller */
-struct mb86r0x_gdc_dsp {
-	/* Display settings */
-	uint32_t dcm0;
-	uint16_t pad00;
-	uint16_t htp;
-	uint16_t hdp;
-	uint16_t hdb;
-	uint16_t hsp;
-	uint8_t  hsw;
-	uint8_t  vsw;
-	uint16_t pad01;
-	uint16_t vtr;
-	uint16_t vsp;
-	uint16_t vdp;
-	uint16_t wx;
-	uint16_t wy;
-	uint16_t ww;
-	uint16_t wh;
-
-	/* Layer 0 */
-	uint32_t l0m;
-	uint32_t l0oa;
-	uint32_t l0da;
-	uint16_t l0dx;
-	uint16_t l0dy;
-
-	/* Layer 1 */
-	uint32_t l1m;
-	uint32_t cbda0;
-	uint32_t cbda1;
-	uint32_t pad02;
-
-	/* Layer 2 */
-	uint32_t l2m;
-	uint32_t l2oa0;
-	uint32_t l2da0;
-	uint32_t l2oa1;
-	uint32_t l2da1;
-	uint16_t l2dx;
-	uint16_t l2dy;
-
-	/* Layer 3 */
-	uint32_t l3m;
-	uint32_t l3oa0;
-	uint32_t l3da0;
-	uint32_t l3oa1;
-	uint32_t l3da1;
-	uint16_t l3dx;
-	uint16_t l3dy;
-
-	/* Layer 4 */
-	uint32_t l4m;
-	uint32_t l4oa0;
-	uint32_t l4da0;
-	uint32_t l4oa1;
-	uint32_t l4da1;
-	uint16_t l4dx;
-	uint16_t l4dy;
-
-	/* Layer 5 */
-	uint32_t l5m;
-	uint32_t l5oa0;
-	uint32_t l5da0;
-	uint32_t l5oa1;
-	uint32_t l5da1;
-	uint16_t l5dx;
-	uint16_t l5dy;
-
-	/* Cursor */
-	uint16_t cutc;
-	uint8_t  cpm;
-	uint8_t  csize;
-	uint32_t cuoa0;
-	uint16_t cux0;
-	uint16_t cuy0;
-	uint32_t cuoa1;
-	uint16_t cux1;
-	uint16_t cuy1;
-
-	/* Layer blending */
-	uint32_t l0bld;
-	uint32_t pad03;
-	uint32_t l0tc;
-	uint16_t l3tc;
-	uint16_t l2tc;
-	uint32_t pad04[15];
-
-	/* Display settings */
-	uint32_t dcm1;
-	uint32_t dcm2;
-	uint32_t dcm3;
-	uint32_t pad05;
-
-	/* Layer 0 extended */
-	uint32_t l0em;
-	uint16_t l0wx;
-	uint16_t l0wy;
-	uint16_t l0ww;
-	uint16_t l0wh;
-	uint32_t pad06;
-
-	/* Layer 1 extended */
-	uint32_t l1em;
-	uint16_t l1wx;
-	uint16_t l1wy;
-	uint16_t l1ww;
-	uint16_t l1wh;
-	uint32_t pad07;
-
-	/* Layer 2 extended */
-	uint32_t l2em;
-	uint16_t l2wx;
-	uint16_t l2wy;
-	uint16_t l2ww;
-	uint16_t l2wh;
-	uint32_t pad08;
-
-	/* Layer 3 extended */
-	uint32_t l3em;
-	uint16_t l3wx;
-	uint16_t l3wy;
-	uint16_t l3ww;
-	uint16_t l3wh;
-	uint32_t pad09;
-
-	/* Layer 4 extended */
-	uint32_t l4em;
-	uint16_t l4wx;
-	uint16_t l4wy;
-	uint16_t l4ww;
-	uint16_t l4wh;
-	uint32_t pad10;
-
-	/* Layer 5 extended */
-	uint32_t l5em;
-	uint16_t l5wx;
-	uint16_t l5wy;
-	uint16_t l5ww;
-	uint16_t l5wh;
-	uint32_t pad11;
-
-	/* Multi screen control */
-	uint32_t msc;
-	uint32_t pad12[3];
-	uint32_t dls;
-	uint32_t dbgc;
-
-	/* Layer blending */
-	uint32_t l1bld;
-	uint32_t l2bld;
-	uint32_t l3bld;
-	uint32_t l4bld;
-	uint32_t l5bld;
-	uint32_t pad13;
-
-	/* Extended transparency control */
-	uint32_t l0etc;
-	uint32_t l1etc;
-	uint32_t l2etc;
-	uint32_t l3etc;
-	uint32_t l4etc;
-	uint32_t l5etc;
-	uint32_t pad14[10];
-
-	/* YUV coefficients */
-	uint32_t l1ycr0;
-	uint32_t l1ycr1;
-	uint32_t l1ycg0;
-	uint32_t l1ycg1;
-	uint32_t l1ycb0;
-	uint32_t l1ycb1;
-	uint32_t pad15[130];
-
-	/* Layer palletes */
-	uint32_t l0pal[256];
-	uint32_t l1pal[256];
-	uint32_t pad16[256];
-	uint32_t l2pal[256];
-	uint32_t l3pal[256];
-	uint32_t pad17[256];
-
-	/* PWM settings */
-	uint32_t vpwmm;
-	uint16_t vpwms;
-	uint16_t vpwme;
-	uint32_t vpwmc;
-	uint32_t pad18[253];
-};
-
-/* mb86r0x gdc capture controller */
-struct mb86r0x_gdc_cap {
-	uint32_t vcm;
-	uint32_t csc;
-	uint32_t vcs;
-	uint32_t pad01;
-
-	uint32_t cbm;
-	uint32_t cboa;
-	uint32_t cbla;
-	uint16_t cihstr;
-	uint16_t civstr;
-	uint16_t cihend;
-	uint16_t civend;
-	uint32_t pad02;
-
-	uint32_t chp;
-	uint32_t cvp;
-	uint32_t pad03[4];
-
-	uint32_t clpf;
-	uint32_t pad04;
-	uint32_t cmss;
-	uint32_t cmds;
-	uint32_t pad05[12];
-
-	uint32_t rgbhc;
-	uint32_t rgbhen;
-	uint32_t rgbven;
-	uint32_t pad06;
-	uint32_t rgbs;
-	uint32_t pad07[11];
-
-	uint32_t rgbcmy;
-	uint32_t rgbcmcb;
-	uint32_t rgbcmcr;
-	uint32_t rgbcmb;
-	uint32_t pad08[12 + 1984];
-};
-
-/* mb86r0x gdc draw */
-struct mb86r0x_gdc_draw {
-	uint32_t ys;
-	uint32_t xs;
-	uint32_t dxdy;
-	uint32_t xus;
-	uint32_t dxudy;
-	uint32_t xls;
-	uint32_t dxldy;
-	uint32_t usn;
-	uint32_t lsn;
-	uint32_t pad01[7];
-	uint32_t rs;
-	uint32_t drdx;
-	uint32_t drdy;
-	uint32_t gs;
-	uint32_t dgdx;
-	uint32_t dgdy;
-	uint32_t bs;
-	uint32_t dbdx;
-	uint32_t dbdy;
-	uint32_t pad02[7];
-	uint32_t zs;
-	uint32_t dzdx;
-	uint32_t dzdy;
-	uint32_t pad03[13];
-	uint32_t ss;
-	uint32_t dsdx;
-	uint32_t dsdy;
-	uint32_t ts;
-	uint32_t dtdx;
-	uint32_t dtdy;
-	uint32_t qs;
-	uint32_t dqdx;
-	uint32_t dqdy;
-	uint32_t pad04[23];
-	uint32_t lpn;
-	uint32_t lxs;
-	uint32_t lxde;
-	uint32_t lys;
-	uint32_t lyde;
-	uint32_t lzs;
-	uint32_t lzde;
-	uint32_t pad05[13];
-	uint32_t pxdc;
-	uint32_t pydc;
-	uint32_t pzdc;
-	uint32_t pad06[25];
-	uint32_t rxs;
-	uint32_t rys;
-	uint32_t rsizex;
-	uint32_t rsizey;
-	uint32_t pad07[12];
-	uint32_t saddr;
-	uint32_t sstride;
-	uint32_t srx;
-	uint32_t sry;
-	uint32_t daddr;
-	uint32_t dstride;
-	uint32_t drx;
-	uint32_t dry;
-	uint32_t brsizex;
-	uint32_t brsizey;
-	uint32_t tcolor;
-	uint32_t pad08[93];
-	uint32_t blpo;
-	uint32_t pad09[7];
-	uint32_t ctr;
-	uint32_t ifsr;
-	uint32_t ifcnt;
-	uint32_t sst;
-	uint32_t ds;
-	uint32_t pst;
-	uint32_t est;
-	uint32_t pad10;
-	uint32_t mdr0;
-	uint32_t mdr1;
-	uint32_t mdr2;
-	uint32_t mdr3;
-	uint32_t mdr4;
-	uint32_t pad14[2];
-	uint32_t mdr7;
-	uint32_t fbr;
-	uint32_t xres;
-	uint32_t zbr;
-	uint32_t tbr;
-	uint32_t pfbr;
-	uint32_t cxmin;
-	uint32_t cxmax;
-	uint32_t cymin;
-	uint32_t cymax;
-	uint32_t txs;
-	uint32_t tis;
-	uint32_t toa;
-	uint32_t sho;
-	uint32_t abr;
-	uint32_t pad15[2];
-	uint32_t fc;
-	uint32_t bc;
-	uint32_t alf;
-	uint32_t blp;
-	uint32_t pad16;
-	uint32_t tbc;
-	uint32_t pad11[42];
-	uint32_t lx0dc;
-	uint32_t ly0dc;
-	uint32_t lx1dc;
-	uint32_t ly1dc;
-	uint32_t pad12[12];
-	uint32_t x0dc;
-	uint32_t y0dc;
-	uint32_t x1dc;
-	uint32_t y1dc;
-	uint32_t x2dc;
-	uint32_t y2dc;
-	uint32_t pad13[666];
-};
-
-/* mb86r0x gdc geometry engine */
-struct mb86r0x_gdc_geom {
-	uint32_t gctr;
-	uint32_t pad00[15];
-	uint32_t gmdr0;
-	uint32_t gmdr1;
-	uint32_t gmdr2;
-	uint32_t pad01[237];
-	uint32_t dfifog;
-	uint32_t pad02[767];
-};
-
-/* mb86r0x gdc */
-struct mb86r0x_gdc {
-	uint32_t pad00[2];
-	uint32_t lts;
-	uint32_t pad01;
-	uint32_t lsta;
-	uint32_t pad02[3];
-	uint32_t ist;
-	uint32_t imask;
-	uint32_t pad03[6];
-	uint32_t lsa;
-	uint32_t lco;
-	uint32_t lreq;
-
-	uint32_t pad04[16*1024 - 19];
-	struct mb86r0x_gdc_dsp dsp0;
-	struct mb86r0x_gdc_dsp dsp1;
-	uint32_t pad05[4*1024 - 2];
-	uint32_t vccc;
-	uint32_t vcsr;
-	struct mb86r0x_gdc_cap cap0;
-	struct mb86r0x_gdc_cap cap1;
-	uint32_t pad06[4*1024];
-	uint32_t texture_base[16*1024];
-	struct mb86r0x_gdc_draw draw;
-	uint32_t pad07[7*1024];
-	struct mb86r0x_gdc_geom geom;
-	uint32_t pad08[7*1024];
-};
-
-/* mb86r0x ddr2c */
-struct mb86r0x_ddr2c {
-	uint16_t dric;
-	uint16_t dric1;
-	uint16_t dric2;
-	uint16_t drca;
-	uint16_t drcm;
-	uint16_t drcst1;
-	uint16_t drcst2;
-	uint16_t drcr;
-	uint16_t pad00[8];
-	uint16_t drcf;
-	uint16_t pad01[7];
-	uint16_t drasr;
-	uint16_t pad02[15];
-	uint16_t drims;
-	uint16_t pad03[7];
-	uint16_t dros;
-	uint16_t pad04;
-	uint16_t dribsodt1;
-	uint16_t dribsocd;
-	uint16_t dribsocd2;
-	uint16_t pad05[3];
-	uint16_t droaba;
-	uint16_t pad06[9];
-	uint16_t drobs;
-	uint16_t pad07[5];
-	uint16_t drimr1;
-	uint16_t drimr2;
-	uint16_t drimr3;
-	uint16_t drimr4;
-	uint16_t droisr1;
-	uint16_t droisr2;
-};
-
-/* mb86r0x memc */
-struct mb86r0x_memc {
-	uint32_t mcfmode[8];
-	uint32_t mcftim[8];
-	uint32_t mcfarea[8];
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Physical Address Defines
- */
-#define MB86R0x_DDR2_BASE		0xf3000000
-#define MB86R0x_GDC_BASE		0xf1fc0000
-#define MB86R0x_CCNT_BASE		0xfff42000
-#define MB86R0x_CAN0_BASE		0xfff54000
-#define MB86R0x_CAN1_BASE		0xfff55000
-#define MB86R0x_I2C0_BASE		0xfff56000
-#define MB86R0x_I2C1_BASE		0xfff57000
-#define MB86R0x_EHCI_BASE		0xfff80000
-#define MB86R0x_OHCI_BASE		0xfff81000
-#define MB86R0x_IRC1_BASE		0xfffb0000
-#define MB86R0x_MEMC_BASE		0xfffc0000
-#define MB86R0x_TIMER_BASE		0xfffe0000
-#define MB86R0x_UART0_BASE		0xfffe1000
-#define MB86R0x_UART1_BASE		0xfffe2000
-#define MB86R0x_IRCE_BASE		0xfffe4000
-#define MB86R0x_CRG_BASE		0xfffe7000
-#define MB86R0x_IRC0_BASE		0xfffe8000
-#define MB86R0x_GPIO_BASE		0xfffe9000
-#define MB86R0x_PWM0_BASE		0xfff41000
-#define MB86R0x_PWM1_BASE		0xfff41100
-
-#define MB86R0x_CRSR_SWRSTREQ 		(1 << 1)
-
-/*
- * Timer register bits
- */
-#define MB86R0x_TIMER_ENABLE		(1 << 7)
-#define MB86R0x_TIMER_MODE_MSK		(1 << 6)
-#define MB86R0x_TIMER_MODE_FR		(0 << 6)
-#define MB86R0x_TIMER_MODE_PD		(1 << 6)
-
-#define MB86R0x_TIMER_INT_EN		(1 << 5)
-#define MB86R0x_TIMER_PRS_MSK		(3 << 2)
-#define MB86R0x_TIMER_PRS_4S		(1 << 2)
-#define MB86R0x_TIMER_PRS_8S		(1 << 3)
-#define MB86R0x_TIMER_SIZE_32		(1 << 1)
-#define MB86R0x_TIMER_ONE_SHT		(1 << 0)
-
-/*
- * Clock reset generator bits
- */
-#define MB86R0x_CRG_CRPR_PLLRDY		(1 << 8)
-#define MB86R0x_CRG_CRPR_PLLMODE	(0x1f << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X49	(0 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X46	(1 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X37	(2 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X20	(3 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X47	(4 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X44	(5 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X36	(6 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X19	(7 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X39	(8 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X38	(9 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X30	(10 << 0)
-#define MB86R0x_CRG_CRPR_PLLMODE_X15	(11 << 0)
-/*
- * DDR2 controller bits
- */
-#define MB86R0x_DDR2_DRCI_DRINI		(1 << 15)
-#define MB86R0x_DDR2_DRCI_CKEN		(1 << 14)
-#define MB86R0x_DDR2_DRCI_DRCMD		(1 << 0)
-#define MB86R0x_DDR2_DRCI_CMD		(MB86R0x_DDR2_DRCI_DRINI | \
-					MB86R0x_DDR2_DRCI_CKEN | \
-					MB86R0x_DDR2_DRCI_DRCMD)
-#define MB86R0x_DDR2_DRCI_INIT		(MB86R0x_DDR2_DRCI_DRINI | \
-					MB86R0x_DDR2_DRCI_CKEN)
-#define MB86R0x_DDR2_DRCI_NORMAL	MB86R0x_DDR2_DRCI_CKEN
-#endif /* MB86R0X_H */
diff --git a/arch/arm/include/asm/arch-nomadik/gpio.h b/arch/arm/include/asm/arch-nomadik/gpio.h
deleted file mode 100644
index 311758ae1a..0000000000
--- a/arch/arm/include/asm/arch-nomadik/gpio.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __NMK_GPIO_H__
-#define __NMK_GPIO_H__
-
-/*
- * These functions are called from the soft-i2c driver, but
- * are also used by board files to set output bits.
- */
-
-enum nmk_af { /* alternate function settings */
-	GPIO_GPIO = 0,
-	GPIO_ALT_A,
-	GPIO_ALT_B,
-	GPIO_ALT_C
-};
-
-extern void nmk_gpio_af(int gpio, int alternate_function);
-extern void nmk_gpio_dir(int gpio, int dir);
-extern void nmk_gpio_set(int gpio, int val);
-extern int nmk_gpio_get(int gpio);
-
-#endif /* __NMK_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-nomadik/mtu.h b/arch/arm/include/asm/arch-nomadik/mtu.h
deleted file mode 100644
index f89f242247..0000000000
--- a/arch/arm/include/asm/arch-nomadik/mtu.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
-#define MTU_RIS		0x04	/* Raw interrupt status */
-#define MTU_MIS		0x08	/* Masked interrupt status */
-#define MTU_ICR		0x0C	/* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
-#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
-#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
-#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA		0x80
-#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK	0x0c
-#define MTU_CRn_PRESCALE_1		0x00
-#define MTU_CRn_PRESCALE_16		0x04
-#define MTU_CRn_PRESCALE_256		0x08
-#define MTU_CRn_32BITS		0x02
-#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR	0xff0
-#define MTU_ITOP	0xff4
-
-#define MTU_PERIPH_ID0	0xfe0
-#define MTU_PERIPH_ID1	0xfe4
-#define MTU_PERIPH_ID2	0xfe8
-#define MTU_PERIPH_ID3	0xfeC
-
-#define MTU_PCELL0	0xff0
-#define MTU_PCELL1	0xff4
-#define MTU_PCELL2	0xff8
-#define MTU_PCELL3	0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
deleted file mode 100644
index 08a450f1f3..0000000000
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirorion5x_ood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ORION5X_CPU_H
-#define _ORION5X_CPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
-			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
-
-#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
-
-enum memory_bank {
-	BANK0,
-	BANK1,
-	BANK2,
-	BANK3
-};
-
-enum orion5x_cpu_winen {
-	ORION5X_WIN_DISABLE,
-	ORION5X_WIN_ENABLE
-};
-
-enum orion5x_cpu_target {
-	ORION5X_TARGET_DRAM = 0,
-	ORION5X_TARGET_DEVICE = 1,
-	ORION5X_TARGET_PCI = 3,
-	ORION5X_TARGET_PCIE = 4,
-	ORION5X_TARGET_SASRAM = 9
-};
-
-enum orion5x_cpu_attrib {
-	ORION5X_ATTR_DRAM_CS0 = 0x0e,
-	ORION5X_ATTR_DRAM_CS1 = 0x0d,
-	ORION5X_ATTR_DRAM_CS2 = 0x0b,
-	ORION5X_ATTR_DRAM_CS3 = 0x07,
-	ORION5X_ATTR_PCI_MEM = 0x59,
-	ORION5X_ATTR_PCI_IO = 0x51,
-	ORION5X_ATTR_PCIE_MEM = 0x59,
-	ORION5X_ATTR_PCIE_IO = 0x51,
-	ORION5X_ATTR_SASRAM = 0x00,
-	ORION5X_ATTR_DEV_CS0 = 0x1e,
-	ORION5X_ATTR_DEV_CS1 = 0x1d,
-	ORION5X_ATTR_DEV_CS2 = 0x1b,
-	ORION5X_ATTR_BOOTROM = 0x0f
-};
-
-/*
- * Device Address MAP BAR values
- *
- * All addresses and sizes not defined by board code
- * will be given default values here.
- */
-
-#if !defined (ORION5X_ADR_PCIE_MEM)
-#define ORION5X_ADR_PCIE_MEM	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO)
-#define ORION5X_ADR_PCIE_MEM_REMAP_LO	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI)
-#define ORION5X_ADR_PCIE_MEM_REMAP_HI	0
-#endif
-
-#if !defined (ORION5X_SZ_PCIE_MEM)
-#define ORION5X_SZ_PCIE_MEM	(128*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO)
-#define ORION5X_ADR_PCIE_IO	0xf0000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO)
-#define ORION5X_ADR_PCIE_IO_REMAP_LO	0x90000000
-#endif
-
-#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI)
-#define ORION5X_ADR_PCIE_IO_REMAP_HI	0
-#endif
-
-#if !defined (ORION5X_SZ_PCIE_IO)
-#define ORION5X_SZ_PCIE_IO	(64*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCI_MEM)
-#define ORION5X_ADR_PCI_MEM	0x98000000
-#endif
-
-#if !defined (ORION5X_SZ_PCI_MEM)
-#define ORION5X_SZ_PCI_MEM	(128*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_PCI_IO)
-#define ORION5X_ADR_PCI_IO	0xf0100000
-#endif
-
-#if !defined (ORION5X_SZ_PCI_IO)
-#define ORION5X_SZ_PCI_IO	(64*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS0)
-#define ORION5X_ADR_DEV_CS0	0xfa000000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS0)
-#define ORION5X_SZ_DEV_CS0	(2*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS1)
-#define ORION5X_ADR_DEV_CS1	0xf8000000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS1)
-#define ORION5X_SZ_DEV_CS1	(32*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_DEV_CS2)
-#define ORION5X_ADR_DEV_CS2	0xfa800000
-#endif
-
-#if !defined (ORION5X_SZ_DEV_CS2)
-#define ORION5X_SZ_DEV_CS2	(1*1024*1024)
-#endif
-
-#if !defined (ORION5X_ADR_BOOTROM)
-#define ORION5X_ADR_BOOTROM	0xFFF80000
-#endif
-
-#if !defined (ORION5X_SZ_BOOTROM)
-#define ORION5X_SZ_BOOTROM	(512*1024)
-#endif
-
-/*
- * PCIE registers are used for SoC device ID and revision
- */
-#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
-#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
-
-/*
- * The following definitions are intended for identifying
- * the real device and revision on which u-boot is running
- * even if it was compiled only for a specific one. Thus,
- * these constants must not be considered chip-specific.
- */
-
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-#define MV88F5181L_REV_A0       8
-#define MV88F5181L_REV_A1       9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D0        4
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-/* Orion-1-90 (88F6183) */
-#define MV88F6183_DEV_ID        0x6183
-#define MV88F6183_REV_B0        3
-
-/*
- * read feroceon core extra feature register
- * using co-proc instruction
- */
-static inline unsigned int readfr_extra_feature_reg(void)
-{
-	unsigned int val;
-	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
-			(val) : : "cc");
-	return val;
-}
-
-/*
- * write feroceon core extra feature register
- * using co-proc instruction
- */
-static inline void writefr_extra_feature_reg(unsigned int val)
-{
-	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
-			(val) : "cc");
-	isb();
-}
-
-/*
- * AHB to Mbus Bridge Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- * Note: only windows 0 and 1 have remap capability.
- */
-struct orion5x_win_registers {
-	u32 ctrl;
-	u32 base;
-	u32 remap_lo;
-	u32 remap_hi;
-};
-
-/*
- * CPU control and status Registers
- * Source: 88F5182 User Manual, Appendix A, section A.4
- */
-struct orion5x_cpu_registers {
-	u32 config;	/*0x20100 */
-	u32 ctrl_stat;	/*0x20104 */
-	u32 rstoutn_mask; /* 0x20108 */
-	u32 sys_soft_rst; /* 0x2010C */
-	u32 ahb_mbus_cause_irq; /* 0x20110 */
-	u32 ahb_mbus_mask_irq; /* 0x20114 */
-};
-
-/*
- * DDR SDRAM Controller Address Decode Registers
- * Source: 88F5182 User Manual, Appendix A, section A.5.1
- */
-struct orion5x_ddr_addr_decode_registers {
-	u32 base;
-	u32 size;
-};
-
-/*
- * functions
- */
-u32 orion5x_device_id(void);
-u32 orion5x_device_rev(void);
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
-void timer_init_r(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _ORION5X_CPU_H */
diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
deleted file mode 100644
index e6c71ae1b3..0000000000
--- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood 88F6182 support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Feroceon CPU core 88F5182 SOC.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CONFIG_88F5182_H
-#define _CONFIG_88F5182_H
-
-/* SOC specific definitions */
-#define F88F5182_REGS_PHYS_BASE		0xf1000000
-#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
-
-/* TCLK Core Clock defination */
-#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
-
-#endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
deleted file mode 100644
index fbb1de8c0d..0000000000
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for Marvell's Orion SoC with Feroceon CPU core.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_ORION5X_H
-#define _ASM_ARCH_ORION5X_H
-
-#if defined(CONFIG_FEROCEON)
-
-/* SOC specific definations */
-#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
-
-/* Documented registers */
-#define ORION5X_DRAM_BASE			(ORION5X_REGISTER(0x01500))
-#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
-#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
-#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
-#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
-#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
-#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
-#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
-#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
-#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
-#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
-#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
-#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
-#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
-#define ORION5X_SATA_BASE			(ORION5X_REGISTER(0x80000))
-#define ORION5X_SATA_PORT0_OFFSET		0x2000
-#define ORION5X_SATA_PORT1_OFFSET		0x4000
-
-/* Orion5x GbE controller has a single port */
-#define MAX_MVGBE_DEVS	1
-#define MVGBE0_BASE	ORION5X_EGIGA_BASE
-
-/* Orion5x USB Host controller is port 1 */
-#define MVUSB0_BASE			ORION5X_USB20_HOST_PORT_BASE
-#define MVUSB0_CPU_ATTR_DRAM_CS0	ORION5X_ATTR_DRAM_CS0
-#define MVUSB0_CPU_ATTR_DRAM_CS1	ORION5X_ATTR_DRAM_CS1
-#define MVUSB0_CPU_ATTR_DRAM_CS2	ORION5X_ATTR_DRAM_CS2
-#define MVUSB0_CPU_ATTR_DRAM_CS3	ORION5X_ATTR_DRAM_CS3
-
-/* Kirkwood CPU memory windows */
-#define MVCPU_WIN_CTRL_DATA	ORION5X_CPU_WIN_CTRL_DATA
-#define MVCPU_WIN_ENABLE	ORION5X_WIN_ENABLE
-#define MVCPU_WIN_DISABLE	ORION5X_WIN_DISABLE
-
-#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
-
-/* include here SoC variants. 5181, 5281, 6183 should go here when
-   adding support for them, and this comment should then be updated. */
-#if defined(CONFIG_88F5182)
-#include <asm/arch/mv88f5182.h>
-#else
-#error "SOC Name not defined"
-#endif
-#endif /* CONFIG_FEROCEON */
-#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644
index 1eed7b1d56..0000000000
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
-#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
-						represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV			1
-#define CONFIG_MV_I2C_REG		0xd4011000
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		0
-#define CONFIG_SYS_I2C_SLAVE		0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT			1
-#define CONFIG_MMC			1
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_SDHCI			1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS	1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	0x1000
-#define CONFIG_MMC_SDMA			1
-#define CONFIG_MV_SDHCI			1
-#define CONFIG_DOS_PARTITION		1
-#define CONFIG_EFI_PARTITION		1
-#define CONFIG_SYS_MMC_NUM		2
-#define CONFIG_SYS_MMC_BASE		{0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644
index 3ccdf8a359..0000000000
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
-	u8 pad0[0x0024];
-	u32 ccgr;	/*0x0024*/
-	u8 pad1[0x0200 - 0x024 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad2[0x1020 - 0x200 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
-	u8 pad0[0x0054];
-	u32 sd1;	/*0x0054*/
-	u8 pad1[0x00e0 - 0x054 - 4];
-	u32 sd3;	/*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
-	u32 uart0;	/*0x000*/
-	u32 uart1;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u8 pad0[0x02c - 0x08 - 4];
-	u32 twsi;	/*0x02c*/
-	u8 pad1[0x034 - 0x2c - 4];
-	u32 timers;	/*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
-	u32 chip_id;		/* Chip Id Reg */
-	u32 pad;
-	u32 cpu_conf;		/* CPU Conf Reg */
-	u32 pad1;
-	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
-	u32 pad2;
-	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
-	u32 mcb_conf;		/* MCB Conf Reg */
-	u32 sys_boot_ctl;	/* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
deleted file mode 100644
index e69de29bb2..0000000000
--- a/arch/arm/include/asm/arch-pantheon/gpio.h
+++ /dev/null
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644
index 7909d53d46..0000000000
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD		(MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD		(MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL		(MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA		(MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7		(MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6		(MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5		(MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4		(MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3		(MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1		(MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0		(MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD		(MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK		(MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD		(MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP		(MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX	117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644
index c3a71bfce4..0000000000
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK	(1<<4)	/* Peripheral Clock Enable */
-#define APMU_AXI_CLK	(1<<3)	/* AXI Clock Enable*/
-#define APMU_PERI_RST	(1<<1)	/* Peripheral Reset */
-#define APMU_AXI_RST	(1<<0)	/* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE	0xB0000000
-#define PANTHEON_TIMER_BASE	0xD4014000
-#define PANTHEON_WD_TIMER_BASE	0xD4080000
-#define PANTHEON_APBC_BASE	0xD4015000
-#define PANTHEON_UART1_BASE	0xD4017000
-#define PANTHEON_UART2_BASE	0xD4018000
-#define PANTHEON_GPIO_BASE	0xD4019000
-#define PANTHEON_MFPR_BASE	0xD401E000
-#define PANTHEON_MPMU_BASE	0xD4050000
-#define PANTHEON_APMU_BASE	0xD4282800
-#define PANTHEON_CPU_BASE	0xD4282C00
-
-#endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index d297ed0f73..c28ee0528f 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
 
 #define PLL1_CFG_DEFAULT	0xa1005000
 
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT	0xa1009900
+#else
 #define PLL6_CFG_DEFAULT	0xa1009911
+#endif
 
 /* nand clock */
 #define NAND_CLK_SRC_OSC24		0
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
index 7ff43e6d3a..aedd1941d5 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -25,31 +25,7 @@
 #endif
 
 unsigned long sunxi_dram_init(void);
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
-{
-	unsigned long tmo = timer_get_us() + 1000000;
-
-	while ((readl(reg) & mask) != val) {
-		if (timer_get_us() > tmo)
-			panic("Timeout initialising DRAM\n");
-	}
-}
-
-/*
- * Test if memory at offset offset matches memory at begin of DRAM
- */
-static inline bool mctl_mem_matches(u32 offset)
-{
-	/* Try to write different values to RAM at two addresses */
-	writel(0, CONFIG_SYS_SDRAM_BASE);
-	writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
-	/* Check if the same value is actually observed when reading back */
-	return readl(CONFIG_SYS_SDRAM_BASE) ==
-	       readl(CONFIG_SYS_SDRAM_BASE + offset);
-}
+void mctl_await_completion(u32 *reg, u32 mask, u32 val);
+bool mctl_mem_matches(u32 offset);
 
 #endif /* _SUNXI_DRAM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
index c3e636e1d9..60a5bd8c85 100644
--- a/arch/arm/include/asm/arch-sunxi/sys_proto.h
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -13,4 +13,14 @@
 
 void sdelay(unsigned long);
 
+/* return_to_fel() - Return to BROM from SPL
+ *
+ * This returns back into the BROM after U-Boot SPL has performed its initial
+ * init. It uses the provided lr and sp to do so.
+ *
+ * @lr:		BROM link register value (return address)
+ * @sp:		BROM stack pointer
+ */
+void return_to_fel(uint32_t lr, uint32_t sp);
+
 #endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
deleted file mode 100644
index dfc3b1bfa5..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * TNETV107X: Clock APIs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
-#define PSC_MDCTL_NEXT_SYNCRST		0x1
-#define PSC_MDCTL_NEXT_DISABLE		0x2
-#define PSC_MDCTL_NEXT_ENABLE		0x3
-
-#define CONFIG_SYS_INT_OSC_FREQ		24000000
-
-#ifndef __ASSEMBLY__
-
-/* PLL identifiers */
-enum pll_type_e {
-	SYS_PLL,
-	TDM_PLL,
-	ETH_PLL
-};
-
-/* PLL configuration data */
-struct pll_init_data {
-	int pll;
-	int internal_osc;
-	unsigned long pll_freq;
-	unsigned long div_freq[10];
-};
-
-void init_plls(int num_pll, struct pll_init_data *config);
-int  lpsc_status(unsigned int mod);
-void lpsc_control(int mod, unsigned long state, int lrstz);
-unsigned long clk_get_rate(unsigned int clk);
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
-int clk_set_rate(unsigned int clk, unsigned long hz);
-
-static inline void clk_enable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
-}
-
-static inline void clk_disable(unsigned int mod)
-{
-	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
-}
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
deleted file mode 100644
index d458e0bdf0..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/hardware.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * TNETV107X: Hardware information
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sizes.h>
-
-#define ASYNC_EMIF_NUM_CS		4
-#define ASYNC_EMIF_MODE_NOR		0
-#define ASYNC_EMIF_MODE_NAND		1
-#define ASYNC_EMIF_MODE_ONENAND		2
-#define ASYNC_EMIF_PRESERVE		-1
-
-struct async_emif_config {
-	unsigned mode;
-	unsigned select_strobe;
-	unsigned extend_wait;
-	unsigned wr_setup;
-	unsigned wr_strobe;
-	unsigned wr_hold;
-	unsigned rd_setup;
-	unsigned rd_strobe;
-	unsigned rd_hold;
-	unsigned turn_around;
-	enum {
-		ASYNC_EMIF_8	= 0,
-		ASYNC_EMIF_16	= 1,
-		ASYNC_EMIF_32	= 2,
-	} width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
-int wdt_start(unsigned long msecs);
-int wdt_stop(void);
-int wdt_kick(void);
-
-#endif
-
-/* Chip configuration unlock codes and registers */
-#define TNETV107X_KICK0		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
-#define TNETV107X_KICK1		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
-#define TNETV107X_PINMUX(n)	(TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
-#define TNETV107X_KICK0_MAGIC	0x83e70b13
-#define TNETV107X_KICK1_MAGIC	0x95a4f1e0
-
-/* Module base addresses */
-#define TNETV107X_TPCC_BASE			0x01C00000
-#define TNETV107X_TPTC0_BASE			0x01C10000
-#define TNETV107X_TPTC1_BASE			0x01C10400
-#define TNETV107X_INTC_BASE			0x03000000
-#define TNETV107X_LCD_CONTROLLER_BASE		0x08030000
-#define TNETV107X_INTD_BASE			0x08038000
-#define TNETV107X_INTD_IPC_BASE			0x08038000
-#define TNETV107X_INTD_FAST_BASE		0x08039000
-#define TNETV107X_INTD_ASYNC_BASE		0x0803A000
-#define TNETV107X_INTD_SLOW_BASE		0x0803B000
-#define TNETV107X_PKA_BASE			0x08040000
-#define TNETV107X_RNG_BASE			0x08044000
-#define TNETV107X_TIMER0_BASE			0x08086500
-#define TNETV107X_TIMER1_BASE			0x08086600
-#define TNETV107X_WDT0_ARM_BASE			0x08086700
-#define TNETV107X_WDT1_DSP_BASE			0x08086800
-#define TNETV107X_CHIP_CONFIG_SYS_BASE		0x08087000
-#define TNETV107X_GPIO_BASE			0x08088000
-#define TNETV107X_UART1_BASE			0x08088400
-#define TNETV107X_TOUCHSCREEN_BASE		0x08088500
-#define TNETV107X_SDIO0_BASE			0x08088700
-#define TNETV107X_SDIO1_BASE			0x08088800
-#define TNETV107X_MDIO_BASE			0x08088900
-#define TNETV107X_KEYPAD_BASE			0x08088A00
-#define TNETV107X_SSP_BASE			0x08088C00
-#define TNETV107X_CLOCK_CONTROL_BASE		0x0808A000
-#define TNETV107X_PSC_BASE			0x0808B000
-#define TNETV107X_TDM0_BASE			0x08100000
-#define TNETV107X_TDM1_BASE			0x08100100
-#define TNETV107X_MCDMA_BASE			0x08108000
-#define TNETV107X_UART0_DMA_BASE		0x08108200
-#define TNETV107X_USBSS_BASE			0x08120000
-#define TNETV107X_VLYNQ_CONTROL_BASE		0x0810D000
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
-#define TNETV107X_VLYNQ_MEM_MAP_BASE		0x0C000000
-#define TNETV107X_IMCOP_BASE			0x01CC0000
-#define TNETV107X_MBX_LITE_BASE			0x07000000
-#define TNETV107X_ETHSS_BASE			0x0803C000
-#define TNETV107X_CPSW_BASE			0x0803C000
-#define TNETV107X_SPF_BASE			0x0803C800
-#define TNETV107X_IOPU_ETHSS_BASE		0x0803D000
-#define TNETV107X_VTP_CNTRL_0			0x0803D800
-#define TNETV107X_VTP_CNTRL_1			0x0803D900
-#define TNETV107X_UART2_DMA_BASE		0x08108400
-#define TNETV107X_INTERNAL_MEMORY		0x20000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
-#define TNETV107X_DDR_EMIF_DATA_BASE		0x80000000
-#define TNETV107X_DDR_EMIF_CONTROL_BASE		0x90000000
-
-/* LPSC module definitions */
-#define TNETV107X_LPSC_ARM			0
-#define TNETV107X_LPSC_GEM			1
-#define TNETV107X_LPSC_DDR2_PHY			2
-#define TNETV107X_LPSC_TPCC			3
-#define TNETV107X_LPSC_TPTC0			4
-#define TNETV107X_LPSC_TPTC1			5
-#define TNETV107X_LPSC_RAM			6
-#define TNETV107X_LPSC_MBX_LITE			7
-#define TNETV107X_LPSC_LCD			8
-#define TNETV107X_LPSC_ETHSS			9
-#define TNETV107X_LPSC_AEMIF			10
-#define TNETV107X_LPSC_CHIP_CFG			11
-#define TNETV107X_LPSC_TSC			12
-#define TNETV107X_LPSC_ROM			13
-#define TNETV107X_LPSC_UART2			14
-#define TNETV107X_LPSC_PKTSEC			15
-#define TNETV107X_LPSC_SECCTL			16
-#define TNETV107X_LPSC_KEYMGR			17
-#define TNETV107X_LPSC_KEYPAD			18
-#define TNETV107X_LPSC_GPIO			19
-#define TNETV107X_LPSC_MDIO			20
-#define TNETV107X_LPSC_SDIO0			21
-#define TNETV107X_LPSC_UART0			22
-#define TNETV107X_LPSC_UART1			23
-#define TNETV107X_LPSC_TIMER0			24
-#define TNETV107X_LPSC_TIMER1			25
-#define TNETV107X_LPSC_WDT_ARM			26
-#define TNETV107X_LPSC_WDT_DSP			27
-#define TNETV107X_LPSC_SSP			28
-#define TNETV107X_LPSC_TDM0			29
-#define TNETV107X_LPSC_VLYNQ			30
-#define TNETV107X_LPSC_MCDMA			31
-#define TNETV107X_LPSC_USB0			32
-#define TNETV107X_LPSC_TDM1			33
-#define TNETV107X_LPSC_DEBUGSS			34
-#define TNETV107X_LPSC_ETHSS_RGMII		35
-#define TNETV107X_LPSC_SYSTEM			36
-#define TNETV107X_LPSC_IMCOP			37
-#define TNETV107X_LPSC_SPARE			38
-#define TNETV107X_LPSC_SDIO1			39
-#define TNETV107X_LPSC_USB1			40
-#define TNETV107X_LPSC_USBSS			41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
-#define TNETV107X_LPSC_MAX			44
-
-/* Interrupt controller */
-#define INTC_GLB_EN			(TNETV107X_INTC_BASE + 0x10)
-#define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
-#define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
deleted file mode 100644
index 3f832c4147..0000000000
--- a/arch/arm/include/asm/arch-tnetv107x/mux.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * TNETV107X: Pinmux APIs
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-struct pin_config {
-	unsigned char reg_index;
-	unsigned char mask_offset;
-	unsigned char mode;
-};
-
-#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
-			{ reg, offset, mux_mode }
-
-int mux_select_pin(short index);
-int mux_select_pins(const short *pins);
-
-enum tnetv107x_pin_mux_index {
-	TNETV107X_PIN_ASR_A00,
-	TNETV107X_PIN_GPIO32,
-	TNETV107X_PIN_ASR_A01,
-	TNETV107X_PIN_GPIO33,
-	TNETV107X_PIN_ASR_A02,
-	TNETV107X_PIN_GPIO34,
-	TNETV107X_PIN_ASR_A03,
-	TNETV107X_PIN_GPIO35,
-	TNETV107X_PIN_ASR_A04,
-	TNETV107X_PIN_GPIO36,
-	TNETV107X_PIN_ASR_A05,
-	TNETV107X_PIN_GPIO37,
-	TNETV107X_PIN_ASR_A06,
-	TNETV107X_PIN_GPIO38,
-	TNETV107X_PIN_ASR_A07,
-	TNETV107X_PIN_GPIO39,
-	TNETV107X_PIN_ASR_A08,
-	TNETV107X_PIN_GPIO40,
-	TNETV107X_PIN_ASR_A09,
-	TNETV107X_PIN_GPIO41,
-	TNETV107X_PIN_ASR_A10,
-	TNETV107X_PIN_GPIO42,
-	TNETV107X_PIN_ASR_A11,
-	TNETV107X_PIN_BOOT_STRP_0,
-	TNETV107X_PIN_ASR_A12,
-	TNETV107X_PIN_BOOT_STRP_1,
-	TNETV107X_PIN_ASR_A13,
-	TNETV107X_PIN_GPIO43,
-	TNETV107X_PIN_ASR_A14,
-	TNETV107X_PIN_GPIO44,
-	TNETV107X_PIN_ASR_A15,
-	TNETV107X_PIN_GPIO45,
-	TNETV107X_PIN_ASR_A16,
-	TNETV107X_PIN_GPIO46,
-	TNETV107X_PIN_ASR_A17,
-	TNETV107X_PIN_GPIO47,
-	TNETV107X_PIN_ASR_A18,
-	TNETV107X_PIN_GPIO48,
-	TNETV107X_PIN_SDIO1_DATA3_0,
-	TNETV107X_PIN_ASR_A19,
-	TNETV107X_PIN_GPIO49,
-	TNETV107X_PIN_SDIO1_DATA2_0,
-	TNETV107X_PIN_ASR_A20,
-	TNETV107X_PIN_GPIO50,
-	TNETV107X_PIN_SDIO1_DATA1_0,
-	TNETV107X_PIN_ASR_A21,
-	TNETV107X_PIN_GPIO51,
-	TNETV107X_PIN_SDIO1_DATA0_0,
-	TNETV107X_PIN_ASR_A22,
-	TNETV107X_PIN_GPIO52,
-	TNETV107X_PIN_SDIO1_CMD_0,
-	TNETV107X_PIN_ASR_A23,
-	TNETV107X_PIN_GPIO53,
-	TNETV107X_PIN_SDIO1_CLK_0,
-	TNETV107X_PIN_ASR_BA_1,
-	TNETV107X_PIN_GPIO54,
-	TNETV107X_PIN_SYS_PLL_CLK,
-	TNETV107X_PIN_ASR_CS0,
-	TNETV107X_PIN_ASR_CS1,
-	TNETV107X_PIN_ASR_CS2,
-	TNETV107X_PIN_TDM_PLL_CLK,
-	TNETV107X_PIN_ASR_CS3,
-	TNETV107X_PIN_ETH_PHY_CLK,
-	TNETV107X_PIN_ASR_D00,
-	TNETV107X_PIN_GPIO55,
-	TNETV107X_PIN_ASR_D01,
-	TNETV107X_PIN_GPIO56,
-	TNETV107X_PIN_ASR_D02,
-	TNETV107X_PIN_GPIO57,
-	TNETV107X_PIN_ASR_D03,
-	TNETV107X_PIN_GPIO58,
-	TNETV107X_PIN_ASR_D04,
-	TNETV107X_PIN_GPIO59_0,
-	TNETV107X_PIN_ASR_D05,
-	TNETV107X_PIN_GPIO60_0,
-	TNETV107X_PIN_ASR_D06,
-	TNETV107X_PIN_GPIO61_0,
-	TNETV107X_PIN_ASR_D07,
-	TNETV107X_PIN_GPIO62_0,
-	TNETV107X_PIN_ASR_D08,
-	TNETV107X_PIN_GPIO63_0,
-	TNETV107X_PIN_ASR_D09,
-	TNETV107X_PIN_GPIO64_0,
-	TNETV107X_PIN_ASR_D10,
-	TNETV107X_PIN_SDIO1_DATA3_1,
-	TNETV107X_PIN_ASR_D11,
-	TNETV107X_PIN_SDIO1_DATA2_1,
-	TNETV107X_PIN_ASR_D12,
-	TNETV107X_PIN_SDIO1_DATA1_1,
-	TNETV107X_PIN_ASR_D13,
-	TNETV107X_PIN_SDIO1_DATA0_1,
-	TNETV107X_PIN_ASR_D14,
-	TNETV107X_PIN_SDIO1_CMD_1,
-	TNETV107X_PIN_ASR_D15,
-	TNETV107X_PIN_SDIO1_CLK_1,
-	TNETV107X_PIN_ASR_OE,
-	TNETV107X_PIN_BOOT_STRP_2,
-	TNETV107X_PIN_ASR_RNW,
-	TNETV107X_PIN_GPIO29_0,
-	TNETV107X_PIN_ASR_WAIT,
-	TNETV107X_PIN_GPIO30_0,
-	TNETV107X_PIN_ASR_WE,
-	TNETV107X_PIN_BOOT_STRP_3,
-	TNETV107X_PIN_ASR_WE_DQM0,
-	TNETV107X_PIN_GPIO31,
-	TNETV107X_PIN_LCD_PD17_0,
-	TNETV107X_PIN_ASR_WE_DQM1,
-	TNETV107X_PIN_ASR_BA0_0,
-	TNETV107X_PIN_VLYNQ_CLK,
-	TNETV107X_PIN_GPIO14,
-	TNETV107X_PIN_LCD_PD19_0,
-	TNETV107X_PIN_VLYNQ_RXD0,
-	TNETV107X_PIN_GPIO15,
-	TNETV107X_PIN_LCD_PD20_0,
-	TNETV107X_PIN_VLYNQ_RXD1,
-	TNETV107X_PIN_GPIO16,
-	TNETV107X_PIN_LCD_PD21_0,
-	TNETV107X_PIN_VLYNQ_TXD0,
-	TNETV107X_PIN_GPIO17,
-	TNETV107X_PIN_LCD_PD22_0,
-	TNETV107X_PIN_VLYNQ_TXD1,
-	TNETV107X_PIN_GPIO18,
-	TNETV107X_PIN_LCD_PD23_0,
-	TNETV107X_PIN_SDIO0_CLK,
-	TNETV107X_PIN_GPIO19,
-	TNETV107X_PIN_SDIO0_CMD,
-	TNETV107X_PIN_GPIO20,
-	TNETV107X_PIN_SDIO0_DATA0,
-	TNETV107X_PIN_GPIO21,
-	TNETV107X_PIN_SDIO0_DATA1,
-	TNETV107X_PIN_GPIO22,
-	TNETV107X_PIN_SDIO0_DATA2,
-	TNETV107X_PIN_GPIO23,
-	TNETV107X_PIN_SDIO0_DATA3,
-	TNETV107X_PIN_GPIO24,
-	TNETV107X_PIN_EMU0,
-	TNETV107X_PIN_EMU1,
-	TNETV107X_PIN_RTCK,
-	TNETV107X_PIN_TRST_N,
-	TNETV107X_PIN_TCK,
-	TNETV107X_PIN_TDI,
-	TNETV107X_PIN_TDO,
-	TNETV107X_PIN_TMS,
-	TNETV107X_PIN_TDM1_CLK,
-	TNETV107X_PIN_TDM1_RX,
-	TNETV107X_PIN_TDM1_TX,
-	TNETV107X_PIN_TDM1_FS,
-	TNETV107X_PIN_KEYPAD_R0,
-	TNETV107X_PIN_KEYPAD_R1,
-	TNETV107X_PIN_KEYPAD_R2,
-	TNETV107X_PIN_KEYPAD_R3,
-	TNETV107X_PIN_KEYPAD_R4,
-	TNETV107X_PIN_KEYPAD_R5,
-	TNETV107X_PIN_KEYPAD_R6,
-	TNETV107X_PIN_GPIO12,
-	TNETV107X_PIN_KEYPAD_R7,
-	TNETV107X_PIN_GPIO10,
-	TNETV107X_PIN_KEYPAD_C0,
-	TNETV107X_PIN_KEYPAD_C1,
-	TNETV107X_PIN_KEYPAD_C2,
-	TNETV107X_PIN_KEYPAD_C3,
-	TNETV107X_PIN_KEYPAD_C4,
-	TNETV107X_PIN_KEYPAD_C5,
-	TNETV107X_PIN_KEYPAD_C6,
-	TNETV107X_PIN_GPIO13,
-	TNETV107X_PIN_TEST_CLK_IN,
-	TNETV107X_PIN_KEYPAD_C7,
-	TNETV107X_PIN_GPIO11,
-	TNETV107X_PIN_SSP0_0,
-	TNETV107X_PIN_SCC_DCLK,
-	TNETV107X_PIN_LCD_PD20_1,
-	TNETV107X_PIN_SSP0_1,
-	TNETV107X_PIN_SCC_CS_N,
-	TNETV107X_PIN_LCD_PD21_1,
-	TNETV107X_PIN_SSP0_2,
-	TNETV107X_PIN_SCC_D,
-	TNETV107X_PIN_LCD_PD22_1,
-	TNETV107X_PIN_SSP0_3,
-	TNETV107X_PIN_SCC_RESETN,
-	TNETV107X_PIN_LCD_PD23_1,
-	TNETV107X_PIN_SSP1_0,
-	TNETV107X_PIN_GPIO25,
-	TNETV107X_PIN_UART2_CTS,
-	TNETV107X_PIN_SSP1_1,
-	TNETV107X_PIN_GPIO26,
-	TNETV107X_PIN_UART2_RD,
-	TNETV107X_PIN_SSP1_2,
-	TNETV107X_PIN_GPIO27,
-	TNETV107X_PIN_UART2_RTS,
-	TNETV107X_PIN_SSP1_3,
-	TNETV107X_PIN_GPIO28,
-	TNETV107X_PIN_UART2_TD,
-	TNETV107X_PIN_UART0_CTS,
-	TNETV107X_PIN_UART0_RD,
-	TNETV107X_PIN_UART0_RTS,
-	TNETV107X_PIN_UART0_TD,
-	TNETV107X_PIN_UART1_RD,
-	TNETV107X_PIN_UART1_TD,
-	TNETV107X_PIN_LCD_AC_NCS,
-	TNETV107X_PIN_LCD_HSYNC_RNW,
-	TNETV107X_PIN_LCD_VSYNC_A0,
-	TNETV107X_PIN_LCD_MCLK,
-	TNETV107X_PIN_LCD_PD16_0,
-	TNETV107X_PIN_LCD_PCLK_E,
-	TNETV107X_PIN_LCD_PD00,
-	TNETV107X_PIN_LCD_PD01,
-	TNETV107X_PIN_LCD_PD02,
-	TNETV107X_PIN_LCD_PD03,
-	TNETV107X_PIN_LCD_PD04,
-	TNETV107X_PIN_LCD_PD05,
-	TNETV107X_PIN_LCD_PD06,
-	TNETV107X_PIN_LCD_PD07,
-	TNETV107X_PIN_LCD_PD08,
-	TNETV107X_PIN_GPIO59_1,
-	TNETV107X_PIN_LCD_PD09,
-	TNETV107X_PIN_GPIO60_1,
-	TNETV107X_PIN_LCD_PD10,
-	TNETV107X_PIN_ASR_BA0_1,
-	TNETV107X_PIN_GPIO61_1,
-	TNETV107X_PIN_LCD_PD11,
-	TNETV107X_PIN_GPIO62_1,
-	TNETV107X_PIN_LCD_PD12,
-	TNETV107X_PIN_GPIO63_1,
-	TNETV107X_PIN_LCD_PD13,
-	TNETV107X_PIN_GPIO64_1,
-	TNETV107X_PIN_LCD_PD14,
-	TNETV107X_PIN_GPIO29_1,
-	TNETV107X_PIN_LCD_PD15,
-	TNETV107X_PIN_GPIO30_1,
-	TNETV107X_PIN_EINT0,
-	TNETV107X_PIN_GPIO08,
-	TNETV107X_PIN_EINT1,
-	TNETV107X_PIN_GPIO09,
-	TNETV107X_PIN_GPIO00,
-	TNETV107X_PIN_LCD_PD20_2,
-	TNETV107X_PIN_TDM_CLK_IN_2,
-	TNETV107X_PIN_GPIO01,
-	TNETV107X_PIN_LCD_PD21_2,
-	TNETV107X_PIN_24M_CLK_OUT_1,
-	TNETV107X_PIN_GPIO02,
-	TNETV107X_PIN_LCD_PD22_2,
-	TNETV107X_PIN_GPIO03,
-	TNETV107X_PIN_LCD_PD23_2,
-	TNETV107X_PIN_GPIO04,
-	TNETV107X_PIN_LCD_PD16_1,
-	TNETV107X_PIN_USB0_RXERR,
-	TNETV107X_PIN_GPIO05,
-	TNETV107X_PIN_LCD_PD17_1,
-	TNETV107X_PIN_TDM_CLK_IN_1,
-	TNETV107X_PIN_GPIO06,
-	TNETV107X_PIN_LCD_PD18,
-	TNETV107X_PIN_24M_CLK_OUT_2,
-	TNETV107X_PIN_GPIO07,
-	TNETV107X_PIN_LCD_PD19_1,
-	TNETV107X_PIN_USB1_RXERR,
-	TNETV107X_PIN_ETH_PLL_CLK,
-	TNETV107X_PIN_MDIO,
-	TNETV107X_PIN_MDC,
-	TNETV107X_PIN_AIC_MUTE_STAT_N,
-	TNETV107X_PIN_TDM0_CLK,
-	TNETV107X_PIN_AIC_HNS_EN_N,
-	TNETV107X_PIN_TDM0_FS,
-	TNETV107X_PIN_AIC_HDS_EN_STAT_N,
-	TNETV107X_PIN_TDM0_TX,
-	TNETV107X_PIN_AIC_HNF_EN_STAT_N,
-	TNETV107X_PIN_TDM0_RX,
-};
-
-#endif
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4b7b67b643..4b9cb52965 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,7 +65,8 @@
 /*
  * Section
  */
-#define PMD_SECT_S		(3 << 8)
+#define PMD_SECT_OUTER_SHARE	(2 << 8)
+#define PMD_SECT_INNER_SHARE	(3 << 8)
 #define PMD_SECT_AF		(1 << 10)
 #define PMD_SECT_NG		(1 << 11)
 #define PMD_SECT_PXN		(UL(1) << 53)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 342f045f41..7a545ea01a 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1149,6 +1149,7 @@ struct emif_regs {
 	u32 sdram_config;
 	u32 sdram_config2;
 	u32 ref_ctrl;
+	u32 ref_ctrl_final;
 	u32 sdram_tim1;
 	u32 sdram_tim2;
 	u32 sdram_tim3;
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 438f128326..bb24f33d0d 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -48,6 +48,9 @@ struct arch_global_data {
 #ifdef CONFIG_OMAP
 	struct omap_boot_parameters omap_boot_params;
 #endif
+#ifdef CONFIG_FSL_LSCH3
+	unsigned long mem2_clk;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 8acd7cd1bd..17b6f544da 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -26,10 +26,14 @@ enum {
 	BOOT_DEVICE_SPI,
 	BOOT_DEVICE_SATA,
 	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
 	BOOT_DEVICE_NONE
 };
 #endif
 
+/* Board-specific load method */
+void spl_board_load_image(void);
+
 /* Linker symbols. */
 extern char __bss_start[], __bss_end[];
 
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 89f2294689..2a5bed2e46 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -70,6 +70,7 @@ void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
 void __asm_invalidate_tlb_all(void);
 void __asm_invalidate_icache_all(void);
+int __asm_flush_l3_cache(void);
 
 void armv8_switch_to_el2(void);
 void armv8_switch_to_el1(void);
@@ -142,6 +143,21 @@ void flush_l3_cache(void);
 
 #ifndef __ASSEMBLY__
 
+/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
 #define isb() __asm__ __volatile__ ("" : : : "memory")
 
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");