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| author | Saksham Jain <saksham.jain@nxp.com> | 2016-03-23 16:24:34 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-03-29 08:46:20 -0700 |
| commit | fd6dbc98a73207ff961f1f83ea833654d98354c3 (patch) | |
| tree | 263678a32fd2c3a5c4af1eef4a9222b0a3ae2628 /arch/arm/include/asm | |
| parent | 2827d64774e7de9680ccd0b283856cc28f78a17f (diff) | |
| download | talos-obmc-uboot-fd6dbc98a73207ff961f1f83ea833654d98354c3.tar.gz talos-obmc-uboot-fd6dbc98a73207ff961f1f83ea833654d98354c3.zip | |
armv8: fsl-lsch3: Add new header for secure boot
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/fsl_secure_boot.h | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 00916f5c71..cc25811fc1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -79,7 +79,8 @@ /* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE - +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index a32a1d7222..4eb3b156c8 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -35,9 +35,13 @@ * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). */ +#ifndef CONFIG_ESBC_HDR_LS +/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif + #ifdef CONFIG_LS1043A /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ #define CONFIG_ESBC_ADDR_64BIT |
