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authorYork Sun <yorksun@freescale.com>2014-06-23 15:15:54 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-07-03 08:40:51 +0200
commit2f78eae5064728d6cd907148cfeaf8ba3e63b0ef (patch)
tree80b5d23e3c6d46424909954cbc9504288e8f7156 /arch/arm/include/asm/system.h
parent22932ffc03e521130cfd33cae1fc2531eb42604a (diff)
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ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/system.h')
-rw-r--r--arch/arm/include/asm/system.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 74ee9a4df9..d51ba668f3 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -78,6 +78,8 @@ void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
void smp_kick_all_cpus(void);
+void flush_l3_cache(void);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
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