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author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-01-29 17:39:49 -0200 |
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committer | Stefano Babic <sbabic@denx.de> | 2014-02-11 11:24:12 +0100 |
commit | 6d73c23410cd0f8a54227dd0361fb8b9eadcb4b2 (patch) | |
tree | 6e1b31648037762e47c487b94a271c14789d5c69 /arch/arm/include/asm/pl310.h | |
parent | 4702c62dce3e2e2648ae3c8d002202211de8c92a (diff) | |
download | talos-obmc-uboot-6d73c23410cd0f8a54227dd0361fb8b9eadcb4b2.tar.gz talos-obmc-uboot-6d73c23410cd0f8a54227dd0361fb8b9eadcb4b2.zip |
mx6: Enable L2 cache support
Add L2 cache support and enable it by default.
Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/pl310.h')
-rw-r--r-- | arch/arm/include/asm/pl310.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f41ad8c559..ddc245bfd5 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -12,6 +12,9 @@ /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) +#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) +#define L2X0_STNDBY_MODE_EN (1 << 0) +#define L2X0_CTRL_EN 1 struct pl310_regs { u32 pl310_cache_id; @@ -47,6 +50,24 @@ struct pl310_regs { u32 pad9[1]; u32 pl310_clean_inv_line_idx; u32 pl310_clean_inv_way; + u32 pad10[64]; + u32 pl310_lockdown_dbase; + u32 pl310_lockdown_ibase; + u32 pad11[190]; + u32 pl310_addr_filter_start; + u32 pl310_addr_filter_end; + u32 pad12[190]; + u32 pl310_test_operation; + u32 pad13[3]; + u32 pl310_line_data; + u32 pad14[7]; + u32 pl310_line_tag; + u32 pad15[3]; + u32 pl310_debug_ctrl; + u32 pad16[7]; + u32 pl310_prefetch_ctrl; + u32 pad17[7]; + u32 pl310_power_ctrl; }; void pl310_inval_all(void); |