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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-03-05 17:32:30 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-14 19:18:47 -0400 |
| commit | e3ce3aa103c9e40415673df70ee62732cdb966c3 (patch) | |
| tree | dbc82cfd76bafe62c246e9aceca54397351aea0e /arch/arm/include/asm/emif.h | |
| parent | 4571c519b4581cffc49f40d4066c328df4d6cdf0 (diff) | |
| download | talos-obmc-uboot-e3ce3aa103c9e40415673df70ee62732cdb966c3.tar.gz talos-obmc-uboot-e3ce3aa103c9e40415673df70ee62732cdb966c3.zip | |
ARM: DRA7: emif: Check for enable bits before updating leveling output
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include/asm/emif.h')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7986e6e794..b03cf5a8c4 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -478,6 +478,12 @@ #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT 25 +#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK (1 << 25) +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT 26 +#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK (1 << 26) +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT 27 +#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK (1 << 27) /* DDR_PHY_CTRL_2 */ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 |
