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authorSricharan R <r.sricharan@ti.com>2013-05-30 03:19:39 +0000
committerTom Rini <trini@ti.com>2013-06-10 08:43:10 -0400
commit92b0482c17acf92f94ac74fd8536fd95d5b64b5e (patch)
tree1b8357119fd332ae53f60e03e3962973347b7958 /arch/arm/include/asm/emif.h
parent97405d843ece2a53e67b801e02ee42005d26e172 (diff)
downloadtalos-obmc-uboot-92b0482c17acf92f94ac74fd8536fd95d5b64b5e.tar.gz
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ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/emif.h')
-rw-r--r--arch/arm/include/asm/emif.h12
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 5f11d7b72e..1b94a99c54 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -581,7 +581,7 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13
+#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@@ -855,13 +855,10 @@ struct dmm_lisa_map_regs {
#define DPD_ENABLE 1
/* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM 0xF
-#else
#define REG_CS_TIM 0x0
-#endif
-#define REG_SR_TIM 0xF
-#define REG_PD_TIM 0xF
+#define REG_SR_TIM 0x0
+#define REG_PD_TIM 0x0
+
/* EMIF_PWR_MGMT_CTRL register */
#define EMIF_PWR_MGMT_CTRL (\
@@ -1113,6 +1110,7 @@ struct emif_regs {
u32 freq;
u32 sdram_config_init;
u32 sdram_config;
+ u32 sdram_config2;
u32 ref_ctrl;
u32 sdram_tim1;
u32 sdram_tim2;
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