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authorSanchayan Maity <maitysanchayan@gmail.com>2015-04-15 16:24:22 +0530
committerTom Rini <trini@konsulko.com>2015-04-23 14:56:08 -0400
commitc7ea243cc095d6510e1a1e3a4969e787a9d41271 (patch)
treed8739e6a0d0b8eed7d4f4f09037e412652872577 /arch/arm/include/asm/arch-vf610/imx-regs.h
parent5db73feb1d3fd0130ce97626bfa75a4287b3380a (diff)
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ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the common place under imx-common. Currently ROW_DIFF and COL_DIFF can be chosen from the board file. The JEDEC timings are specified using a common ddr3_jedec_timings structure. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 6b10bdf961..866b30372d 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -196,8 +196,8 @@
#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
#define DDRMC_CR97_WRLVL_EN (1 << 24)
-#define DDRMC_CR98_WRLVL_DL_0 (0)
-#define DDRMC_CR99_WRLVL_DL_1 (0)
+#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff)
+#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff)
#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16)
#define DDRMC_CR102_RDLVL_REG_EN (1 << 8)
#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
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