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authorStephen Warren <swarren@nvidia.com>2014-03-21 12:28:54 -0600
committerTom Warren <twarren@nvidia.com>2014-04-17 08:41:05 -0700
commite296995767e645ed047bcbec90923297a24d4d5a (patch)
tree0ff4f2cf5c6982a2cd2f5fe9d05db5d26ad9dc59 /arch/arm/include/asm/arch-tegra124
parent19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb (diff)
downloadtalos-obmc-uboot-e296995767e645ed047bcbec90923297a24d4d5a.tar.gz
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ARM: tegra: pinctrl: remove duplication
Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra124')
-rw-r--r--arch/arm/include/asm/arch-tegra124/pinmux.h216
1 files changed, 6 insertions, 210 deletions
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 900cf44622..2c6f0d8e60 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -374,7 +374,7 @@ enum pmux_func {
PMUX_FUNC_RESET_OUT_N,
/* End of Tegra114 MUX selectors */
- PMUX_FUNC_MAX,
+ PMUX_FUNC_COUNT,
PMUX_FUNC_INVALID = 0x4000,
PMUX_FUNC_RSVD1 = 0x8000,
@@ -383,213 +383,9 @@ enum pmux_func {
PMUX_FUNC_RSVD4 = 0x8003,
};
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
- (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_PADGRPS
+#include <asm/arch-tegra/pinmux.h>
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && \
- ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* Tegra124 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
-};
-
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
-
-#endif /* _TEGRA124_PINMUX_H_ */
+#endif /* _TEGRA124_PINMUX_H_ */
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