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| author | Simon Glass <sjg@chromium.org> | 2015-04-14 21:03:34 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-05-13 09:24:09 -0700 |
| commit | 96e82a253a4c3a122de5023d9ca5fe04d9e19502 (patch) | |
| tree | c6fa11ecd9601ba006d23c83b060a99151029af6 /arch/arm/include/asm/arch-tegra124/clock.h | |
| parent | 7bb6199bd6c95c89bb9b8e2e2890223e2bca6595 (diff) | |
| download | talos-obmc-uboot-96e82a253a4c3a122de5023d9ca5fe04d9e19502.tar.gz talos-obmc-uboot-96e82a253a4c3a122de5023d9ca5fe04d9e19502.zip | |
tegra124: clock: Add display clocks and functions
Add functions to provide access to the display clocks on Tegra124 including
setting the clock rate for an EDP display.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra124/clock.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/clock.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index 8e65086252..e202cc5a7f 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,27 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + int tegra_plle_enable(void); +void clock_sor_enable_edp_clock(void); + +/** + * clock_set_display_rate() - Set the display clock rate + * + * @frequency: the requested PLLD frequency + * + * Return the PLLD frequenc (which may not quite what was requested), or 0 + * on failure + */ +u32 clock_set_display_rate(u32 frequency); + +/** + * clock_set_up_plldp() - Set up the EDP clock ready for use + */ +void clock_set_up_plldp(void); + #endif /* _TEGRA124_CLOCK_H_ */ |
