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authorAlban Bedel <alban.bedel@avionic-design.de>2013-11-20 17:42:46 +0100
committerTom Warren <twarren@nvidia.com>2013-12-18 10:19:49 -0700
commit766afc3dff35f8f257deb0373735a328c8206880 (patch)
tree2813b7f9f6934e88dcb4831f49474eafd0837842 /arch/arm/include/asm/arch-tegra/clock.h
parent8f38038193752d3719f39ccd562f7ffdf83989d5 (diff)
downloadtalos-obmc-uboot-766afc3dff35f8f257deb0373735a328c8206880.tar.gz
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arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clock.h')
-rw-r--r--arch/arm/include/asm/arch-tegra/clock.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c3174bd7fc..e7d0fd45ee 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
- crc_rst_de = 1 << 2, /* What is de? */
- crc_rst_watchdog = 1 << 3,
- crc_rst_debug = 1 << 4,
+ crc_rst_de = 1 << 4, /* What is de? */
+ crc_rst_watchdog = 1 << 8,
+ crc_rst_debug = 1 << 12,
};
/**
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