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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-02-12 01:33:45 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:11 -0400 |
| commit | d4d986ee27fe6a78e50d4789d5b08b87a5e64892 (patch) | |
| tree | 0bc6adb8e8d303a5512194a6f5cb4a426e678079 /arch/arm/include/asm/arch-omap5/sys_proto.h | |
| parent | 9100edecf8379c357037c34044757202f85480b2 (diff) | |
| download | talos-obmc-uboot-d4d986ee27fe6a78e50d4789d5b08b87a5e64892.tar.gz talos-obmc-uboot-d4d986ee27fe6a78e50d4789d5b08b87a5e64892.zip | |
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
The 1 in wkup domain is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/sys_proto.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/sys_proto.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 201ed6f027..b8d841d3ed 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -59,6 +59,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void); /* * This is used to verify if the configuration header |
