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| author | Nishanth Menon <nm@ti.com> | 2013-05-30 03:19:31 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-10 08:43:10 -0400 |
| commit | 18c9d55ac611784d161440bb9f127e372e132856 (patch) | |
| tree | 85e31364c96bdd69d1d582cf05d8b29da0d6cd84 /arch/arm/include/asm/arch-omap5/clock.h | |
| parent | 3332b244214d63dcf347fefb700fd71becb4b46e (diff) | |
| download | talos-obmc-uboot-18c9d55ac611784d161440bb9f127e372e132856.tar.gz talos-obmc-uboot-18c9d55ac611784d161440bb9f127e372e132856.zip | |
ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/clock.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f7ddd5ffe5..6d02835ead 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -219,6 +219,36 @@ #define VDD_CORE_DRA752 1030 #define VDD_IVA_DRA752 1060 +/* Efuse register offsets for DRA7xx platform */ +#define DRA752_EFUSE_BASE 0x4A002000 +#define DRA752_EFUSE_REGBITS 16 +/* STD_FUSE_OPP_VMIN_IVA_2 */ +#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) +/* STD_FUSE_OPP_VMIN_IVA_3 */ +#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) +/* STD_FUSE_OPP_VMIN_IVA_4 */ +#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) +/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) +/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) +/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) +/* STD_FUSE_OPP_VMIN_CORE_2 */ +#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) +/* STD_FUSE_OPP_VMIN_GPU_2 */ +#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) +/* STD_FUSE_OPP_VMIN_GPU_3 */ +#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) +/* STD_FUSE_OPP_VMIN_GPU_4 */ +#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) +/* STD_FUSE_OPP_VMIN_MPU_2 */ +#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) +/* STD_FUSE_OPP_VMIN_MPU_3 */ +#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) +/* STD_FUSE_OPP_VMIN_MPU_4 */ +#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 |
