ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

3 files changed, 0 insertions, 54 deletions

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index ed7a1c8be7..f544edfbd0 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -34,25 +34,6 @@
  */
 #define LDELAY		1000000
 
-#define CM_CLKMODE_DPLL_CORE		0x4A004120
-#define CM_CLKMODE_DPLL_PER		0x4A008140
-#define CM_CLKMODE_DPLL_MPU		0x4A004160
-#define CM_CLKSEL_CORE			0x4A004100
-
-/* DPLL register offsets */
-#define CM_CLKMODE_DPLL		0
-#define CM_IDLEST_DPLL		0x4
-#define CM_AUTOIDLE_DPLL	0x8
-#define CM_CLKSEL_DPLL		0xC
-#define CM_DIV_M2_DPLL		0x10
-#define CM_DIV_M3_DPLL		0x14
-#define CM_DIV_M4_DPLL		0x18
-#define CM_DIV_M5_DPLL		0x1C
-#define CM_DIV_M6_DPLL		0x20
-#define CM_DIV_M7_DPLL		0x24
-
-#define DPLL_CLKOUT_DIV_MASK	0x1F /* post-divider mask */
-
 /* CM_DLL_CTRL */
 #define CM_DLL_CTRL_OVERRIDE_SHIFT	0
 #define CM_DLL_CTRL_OVERRIDE_MASK	(1 << 0)
@@ -94,8 +75,6 @@
 #define CM_CLKSEL_DCC_EN_SHIFT			22
 #define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
 
-#define OMAP4_DPLL_MAX_N	127
-
 /* CM_SYS_CLKSEL */
 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK	7
 
@@ -181,9 +160,7 @@
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
 
 /* Clock frequencies */
-#define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
-#define OMAP_32K_CLK_FREQ		32768
 
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
@@ -234,11 +211,6 @@
 
 #define ALTCLKSRC_MODE_ACTIVE		1
 
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
-
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 3a0bfbf0c6..311c6ff522 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -115,18 +115,6 @@ struct watchdog {
 #define WD_UNLOCK1		0xAAAA
 #define WD_UNLOCK2		0x5555
 
-#define SYSCLKDIV_1		(0x1 << 6)
-#define SYSCLKDIV_2		(0x1 << 7)
-
-#define CLKSEL_GPT1		(0x1 << 0)
-
-#define EN_GPT1			(0x1 << 0)
-#define EN_32KSYNC		(0x1 << 2)
-
-#define ST_WDT2			(0x1 << 5)
-
-#define RESETDONE		(0x1 << 0)
-
 #define TCLR_ST			(0x1 << 0)
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 55a07605b8..66afd92492 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -47,14 +47,6 @@
 #define DRAM_ADDR_SPACE_START	OMAP44XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END	OMAP44XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE	0x4A100638
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		0x4A002204
 
@@ -79,15 +71,9 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE	(OMAP44XX_L4_WKUP_BASE + 0x4000)
-
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE	0x4A002000
-
 /*
  * Hardware Register Details
  */