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| author | Aneesh V <aneesh@ti.com> | 2011-07-21 09:29:32 -0400 |
|---|---|---|
| committer | U-Boot <uboot@aari01-12.(none)> | 2011-08-03 12:49:20 +0200 |
| commit | d506719f7f83f501ff9c6566831a58ec2bbcc978 (patch) | |
| tree | aa2002ae81a5860c849095ea3c437a73913f23e4 /arch/arm/include/asm/arch-omap4/clocks.h | |
| parent | 25223a68e5f7cc32eebb44313efe8ff15a0f5fd6 (diff) | |
| download | talos-obmc-uboot-d506719f7f83f501ff9c6566831a58ec2bbcc978.tar.gz talos-obmc-uboot-d506719f7f83f501ff9c6566831a58ec2bbcc978.zip | |
omap4: support TPS programming
TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.
VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap4/clocks.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/clocks.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 37bdceebed..5d9cb50c69 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -618,6 +618,7 @@ struct omap4_prcm_regs { #define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 #define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF +/* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B @@ -626,6 +627,21 @@ struct omap4_prcm_regs { #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + /* Defines for DPLL setup */ #define DPLL_LOCKED_FREQ_TOLERANCE_0 0 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 |
