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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2012-05-22 00:03:26 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:24 +0200 |
| commit | 753bae8c5dd4ba92a39b06ea9a551be962053f93 (patch) | |
| tree | 39a9614f4f53620d8f5d3c42aa7d98f1f04b46f1 /arch/arm/include/asm/arch-omap4/clocks.h | |
| parent | 784ab7c545d25288a82216d18e2b0ca3beae470b (diff) | |
| download | talos-obmc-uboot-753bae8c5dd4ba92a39b06ea9a551be962053f93.tar.gz talos-obmc-uboot-753bae8c5dd4ba92a39b06ea9a551be962053f93.zip | |
OMAP5: DPLL core lock for OMAP5432
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap4/clocks.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/clocks.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 617729c32b..be20fc0ce6 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -525,6 +525,11 @@ struct omap4_scrm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) |
