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| author | Heiko Schocher <hs@denx.de> | 2015-05-18 10:56:24 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-05-26 14:16:54 +0200 |
| commit | 21a26940f9048e668f9a79f64b802406b2e8d18c (patch) | |
| tree | 69ad60b6af602381609ecfc3760755757031dc20 /arch/arm/include/asm/arch-mx6 | |
| parent | ab87fc6bbd80f4e702e7dde102b1c74f0f4678b3 (diff) | |
| download | talos-obmc-uboot-21a26940f9048e668f9a79f64b802406b2e8d18c.tar.gz talos-obmc-uboot-21a26940f9048e668f9a79f64b802406b2e8d18c.zip | |
arm, imx6, i2c: add I2C4 for MX6DL
add I2C4 modul for MX6DL based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 0592ce0171..887d04850f 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -592,6 +592,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35bb005552..0d38d450da 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -277,6 +277,7 @@ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) |
