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authorClaudiu Manoil <claudiu.manoil@freescale.com>2015-08-12 13:29:14 +0300
committerYork Sun <yorksun@freescale.com>2015-09-01 21:39:03 -0500
commitebe4c1e6469444753bd2ba93fe63e6183cf2905c (patch)
treecec6f84bbbdf284f6abceb121663b07b2f4b2a61 /arch/arm/include/asm/arch-ls102xa
parentda2919b4a904411c374a6e0d9dc771e180968266 (diff)
downloadtalos-obmc-uboot-ebe4c1e6469444753bd2ba93fe63e6183cf2905c.tar.gz
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ls102xa: etsec: Use proper settings for BE BDs
Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa')
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index d34044a5f7..60aa0d3b6f 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -143,7 +143,7 @@ struct ccsr_gur {
u32 sdhcpcr;
};
-#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
+#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
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