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| author | Tom Rini <trini@ti.com> | 2015-02-25 18:14:18 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-02-25 18:14:18 -0500 |
| commit | 1606b34aa50804227806971dbb6b82ea0bf81f55 (patch) | |
| tree | 5c7570722616c6509f6f9126521d0c69c2614f8d /arch/arm/include/asm/arch-ls102xa/config.h | |
| parent | 47d8ae4069b47ce966c0c5e0d8dd041e69ee1f86 (diff) | |
| parent | 94e3c8c4fd7bfe395fa467973cd647551d6d98c7 (diff) | |
| download | talos-obmc-uboot-1606b34aa50804227806971dbb6b82ea0bf81f55.tar.gz talos-obmc-uboot-1606b34aa50804227806971dbb6b82ea0bf81f55.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa/config.h')
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 791551841c..3b6a1696d8 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,6 +36,7 @@ #define CONFIG_SYS_LS102XA_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 @@ -61,6 +62,20 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +/* + * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) + * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. + */ +#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ + CONFIG_SYS_PCIE1_VIRT_ADDR) +#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ + CONFIG_SYS_PCIE2_VIRT_ADDR) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM |
