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authorAlbert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr>2015-03-31 11:40:44 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2015-04-10 14:22:56 +0200
commitc8381bf435ddb104594df00411a8ebd049dd753c (patch)
tree0269cb43c5534f7985930f02cf898ee15940b072 /arch/arm/include/asm/arch-lpc32xx
parentac2916a2245d999006585b6bb1e312639fa4929b (diff)
downloadtalos-obmc-uboot-c8381bf435ddb104594df00411a8ebd049dd753c.tar.gz
talos-obmc-uboot-c8381bf435ddb104594df00411a8ebd049dd753c.zip
lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Diffstat (limited to 'arch/arm/include/asm/arch-lpc32xx')
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/clk.h4
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/sys_proto.h1
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15f20..bc7d33da01 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 << 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 << 1)
+#define CLK_NAND_MLC_INT (1 << 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826ef5..0c4e712a06 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
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