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| author | Albert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr> | 2015-03-31 11:40:47 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:23:20 +0200 |
| commit | 981219eebe3cc29f155a37951788c18786260514 (patch) | |
| tree | 00085f2e4a1f7834674720f636a6a82a06e3d897 /arch/arm/include/asm/arch-lpc32xx | |
| parent | 606f7047603422746d112e41937649d44f311af4 (diff) | |
| download | talos-obmc-uboot-981219eebe3cc29f155a37951788c18786260514.tar.gz talos-obmc-uboot-981219eebe3cc29f155a37951788c18786260514.zip | |
lpc32xx: add LPC32xx SSP support (SPI mode)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Diffstat (limited to 'arch/arm/include/asm/arch-lpc32xx')
| -rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/clk.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 781ac07103..2cb5703877 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -155,6 +155,9 @@ struct clk_pm_regs { #define CLK_NAND_MLC (1 << 1) #define CLK_NAND_MLC_INT (1 << 5) +/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index a4a05d1ea4..86d5ee9b05 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void); #endif /* _LPC32XX_SYS_PROTO_H */ |
