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authorSylvain Lemieux <slemieux@tycoint.com>2015-09-09 11:35:58 -0400
committerTom Rini <trini@konsulko.com>2015-09-11 17:15:34 -0400
commit89983478bdc99996bbc26bd63fd00358d3082cbe (patch)
tree3c6ce23b11d1eda37728c221790585449cb15037 /arch/arm/include/asm/arch-lpc32xx
parentf3b44e8b2735a542cd962c74e8bc2dd50a87ab67 (diff)
downloadtalos-obmc-uboot-89983478bdc99996bbc26bd63fd00358d3082cbe.tar.gz
talos-obmc-uboot-89983478bdc99996bbc26bd63fd00358d3082cbe.zip
gpio: lpc32xx: fix issues with port3 gpio
The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Diffstat (limited to 'arch/arm/include/asm/arch-lpc32xx')
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio_grp.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
index c9cf9df7cb..64acf150a3 100644
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
@@ -12,7 +12,7 @@
/*
* Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127;
+ * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
@@ -26,9 +26,9 @@
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPI_P3_GRP 96
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
+#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro
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