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| author | Tom Rini <trini@ti.com> | 2012-05-29 09:02:15 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:11 +0200 |
| commit | 7d5eb34908d3a7318d1a3f4afb2c926066a2befc (patch) | |
| tree | d42fc9dfe6ef76aef445f3a5d431aeee0f34d9b5 /arch/arm/include/asm/arch-am33xx/ddr_defs.h | |
| parent | 79b3e6b75b717595ea8cf3f3991a2108d1bbd3a7 (diff) | |
| download | talos-obmc-uboot-7d5eb34908d3a7318d1a3f4afb2c926066a2befc.tar.gz talos-obmc-uboot-7d5eb34908d3a7318d1a3f4afb2c926066a2befc.zip | |
am33xx: Convert to using <asm/emif.h> to describe the EMIF
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/ddr_defs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 388336f9d7..c62f826f78 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -56,33 +56,6 @@ #define DDR_IOCTRL_VALUE 0x18B /** - * This structure represents the EMIF registers on AM33XX devices. - */ -struct emif_regs { - unsigned int sdrrev; /* offset 0x00 */ - unsigned int sdrstat; /* offset 0x04 */ - unsigned int sdrcr; /* offset 0x08 */ - unsigned int sdrcr2; /* offset 0x0C */ - unsigned int sdrrcr; /* offset 0x10 */ - unsigned int sdrrcsr; /* offset 0x14 */ - unsigned int sdrtim1; /* offset 0x18 */ - unsigned int sdrtim1sr; /* offset 0x1C */ - unsigned int sdrtim2; /* offset 0x20 */ - unsigned int sdrtim2sr; /* offset 0x24 */ - unsigned int sdrtim3; /* offset 0x28 */ - unsigned int sdrtim3sr; /* offset 0x2C */ - unsigned int res1[2]; - unsigned int sdrmcr; /* offset 0x38 */ - unsigned int sdrmcsr; /* offset 0x3C */ - unsigned int res2[8]; - unsigned int sdritr; /* offset 0x60 */ - unsigned int res3[32]; - unsigned int ddrphycr; /* offset 0xE4 */ - unsigned int ddrphycsr; /* offset 0xE8 */ - unsigned int ddrphycr2; /* offset 0xEC */ -}; - -/** * Encapsulates DDR PHY control and corresponding shadow registers. */ struct ddr_phy_control { |
