diff options
| author | Cooper Jr., Franklin <fcooper@ti.com> | 2014-06-27 13:31:15 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-07 19:42:34 -0400 |
| commit | 8038b497e742af2845523ed09b560bfc8cb42089 (patch) | |
| tree | baafb8646191200cd64ad7e49faabd77b7d6fe58 /arch/arm/include/asm/arch-am33xx/cpu.h | |
| parent | 2c95211167091e543e20f4f457d3d1f1f660a6d4 (diff) | |
| download | talos-obmc-uboot-8038b497e742af2845523ed09b560bfc8cb42089.tar.gz talos-obmc-uboot-8038b497e742af2845523ed09b560bfc8cb42089.zip | |
am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur.
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/cpu.h')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index aa10fab4dd..8dd69b3c80 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -489,6 +489,12 @@ struct ctrl_stat { #define OMAP_GPIO_SETDATAOUT 0x0194 /* Control Device Register */ + + /* Control Device Register */ +#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F +#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8 +#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F + struct ctrl_dev { unsigned int deviceid; /* offset 0x00 */ unsigned int resv1[7]; @@ -502,10 +508,25 @@ struct ctrl_dev { unsigned int macid1h; /* offset 0x3c */ unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ - unsigned int resv5[106]; + unsigned int resv5[7]; + unsigned int mreqprio_0; /* offset 0x70 */ + unsigned int mreqprio_1; /* offset 0x74 */ + unsigned int resv6[97]; unsigned int efuse_sma; /* offset 0x1FC */ }; +/* Bandwidth Limiter Portion of the L3Fast Configuration Register */ +#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0 +#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0 +#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800 + +struct l3f_cfg_bwlimiter { + u32 padding0[2]; + u32 modena_init0_bw_fractional; + u32 modena_init0_bw_integer; + u32 modena_init0_watermark_0; +}; + /* gmii_sel register defines */ #define GMII1_SEL_MII 0x0 #define GMII1_SEL_RMII 0x1 |
