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| author | Nishanth Menon <nm@ti.com> | 2015-03-09 17:12:03 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-13 09:28:55 -0400 |
| commit | 6d8abe6a8a5981685687a0f2fd660e034d974824 (patch) | |
| tree | 374b51e0afea70f54fecf878efb89715da66d279 /arch/arm/cpu | |
| parent | 9b4d65f918dd84a479552b86ef2cde389926738f (diff) | |
| download | talos-obmc-uboot-6d8abe6a8a5981685687a0f2fd660e034d974824.tar.gz talos-obmc-uboot-6d8abe6a8a5981685687a0f2fd660e034d974824.zip | |
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 18 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/hwinit.c | 4 |
2 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index e19c7aecec..80619b04df 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,15 @@ ENTRY(save_boot_params) b save_boot_params_ret ENDPROC(save_boot_params) -ENTRY(set_pl310_ctrl_reg) - PUSH {r4-r11, lr} @ save registers - ROM code may pollute +ENTRY(omap_smc1) + PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - LDR r12, =0x102 @ Set PL310 control register - value in R0 - .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 - @ call ROM Code API to set control register - POP {r4-r11, pc} -ENDPROC(set_pl310_ctrl_reg) + MOV r12, r0 @ Service + MOV r0, r1 @ Argument + DSB + DMB + .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions + @ call ROM Code API for the service requested + + POP {r4-r12, pc} +ENDPROC(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index db16548fac..9792761d40 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -159,11 +159,11 @@ void init_omap_revision(void) #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { - set_pl310_ctrl_reg(1); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); } void v7_outer_cache_disable(void) { - set_pl310_ctrl_reg(0); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ |
