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authorPraveen Rao <prao@ti.com>2015-03-09 17:12:06 -0500
committerTom Rini <trini@konsulko.com>2015-03-13 09:29:01 -0400
commit5f603761c3de00423cad405e064cd2fc822feab1 (patch)
treeb4a5ed5a564c806d6fbee7f8f93e87cae55f81d2 /arch/arm/cpu
parent49ec9490918909c9694b8ee64789f1eed335df1b (diff)
downloadtalos-obmc-uboot-5f603761c3de00423cad405e064cd2fc822feab1.tar.gz
talos-obmc-uboot-5f603761c3de00423cad405e064cd2fc822feab1.zip
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index a8a474a88b..f8060555b6 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -381,3 +381,10 @@ void setup_warmreset_time(void)
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
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