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authorLinus Walleij <linus.walleij@linaro.org>2015-03-09 10:53:21 +0100
committerTom Rini <trini@konsulko.com>2015-03-09 11:13:29 -0400
commit23b5877c64562a314f8d8c60d0066cd346f2d886 (patch)
tree637ae686c8cda5a7c7d28216bf7d4c1f79f0f945 /arch/arm/cpu
parent671fa63e79053c33456c198c1e0f74262b0b2548 (diff)
downloadtalos-obmc-uboot-23b5877c64562a314f8d8c60d0066cd346f2d886.tar.gz
talos-obmc-uboot-23b5877c64562a314f8d8c60d0066cd346f2d886.zip
armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/Kconfig6
-rw-r--r--arch/arm/cpu/armv8/start.S19
2 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644
index 0000000000..4cd84b0311
--- /dev/null
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -0,0 +1,6 @@
+if ARM64
+
+config ARMV8_MULTIENTRY
+ boolean "Enable multiple CPUs to enter into U-boot"
+
+endif
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f22..df80a4e5fd 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
/* Processor specific initialization */
bl lowlevel_init
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, master_cpu
/*
@@ -88,11 +89,10 @@ slave_cpu:
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
-
- /*
- * Master CPU
- */
master_cpu:
+ /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
bl _main
/*-----------------------------------------------------------------------*/
@@ -100,6 +100,15 @@ master_cpu:
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
+#ifndef CONFIG_ARMV8_MULTIENTRY
+ /*
+ * For single-entry systems the lowlevel init is very simple.
+ */
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
@@ -137,6 +146,8 @@ WEAK(lowlevel_init)
bl armv8_switch_to_el1
#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
2:
mov lr, x29 /* Restore LR */
ret
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