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authorGerlando Falauto <gerlando.falauto@keymile.com>2012-07-20 02:34:25 +0000
committerPrafulla Wadaskar <prafulla@marvell.com>2012-10-03 16:43:13 +0530
commit455151652524570d7c5b320718c7004e63e01656 (patch)
treee7e4b8fc9d5bf69aefa2fa18e62aab2aeee52b05 /arch/arm/cpu
parentcf37c5d98bb2e23fbcbca8a0328ca7dd43d6af8c (diff)
downloadtalos-obmc-uboot-455151652524570d7c5b320718c7004e63e01656.tar.gz
talos-obmc-uboot-455151652524570d7c5b320718c7004e63e01656.zip
kirkwood: implement kw_sdram_bs_set()
Some boards might be equipped with different SDRAM configurations. When that is the case, CPU CS Window Size Register (CS[0]n Size) should be set to the biggest value through board.cfg file; then its value can be fixed at runtime according to the detected SDRAM size. Therefore, implement kw_sdram_bs_set(). Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Marek Vasut <marex@denx.de> Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/dram.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 1c5faabb45..5e2f9d80ea 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -39,6 +39,11 @@ struct kw_sdram_addr_dec {
struct kw_sdram_bank sdram_bank[4];
};
+#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
+#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+
/*
* kw_sdram_bar - reads SDRAM Base Address Register
*/
@@ -57,6 +62,25 @@ u32 kw_sdram_bar(enum memory_bank bank)
}
/*
+ * kw_sdram_bs_set - writes SDRAM Bank size
+ */
+static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+ struct kw_sdram_addr_dec *base =
+ (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+ /* Read current register value */
+ u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+ /* Clear window size */
+ reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+
+ /* Set new window size */
+ reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+ writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
+/*
* kw_sdram_bs - reads SDRAM Bank size
*/
u32 kw_sdram_bs(enum memory_bank bank)
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