diff options
| author | Simon Glass <sjg@chromium.org> | 2016-05-05 07:28:06 -0600 |
|---|---|---|
| committer | Andreas Bießmann <andreas@biessmann.org> | 2016-06-12 23:49:38 +0200 |
| commit | b5bd09820c79dc92b3e5fb5be4b47ce22c731443 (patch) | |
| tree | 6a5fe76224aed2accdc889e21ae4f5d91c31d4bd /arch/arm/cpu/sa1100/start.S | |
| parent | 909584665546ec51c54ac7d362f91fdabaef2cc2 (diff) | |
| download | talos-obmc-uboot-b5bd09820c79dc92b3e5fb5be4b47ce22c731443.tar.gz talos-obmc-uboot-b5bd09820c79dc92b3e5fb5be4b47ce22c731443.zip | |
arm: Allow skipping of low-level init with I-cache on
At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.
What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Diffstat (limited to 'arch/arm/cpu/sa1100/start.S')
| -rw-r--r-- | arch/arm/cpu/sa1100/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 408b70dbc1..f5318c90d1 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -96,6 +96,7 @@ cpu_init_crit: ldr r1, cpuspeed str r1, [r0, #PPCR] +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -104,6 +105,7 @@ cpu_init_crit: mov ip, lr bl lowlevel_init mov lr, ip +#endif /* * disable MMU stuff and enable I-cache |
