path: root/arch/arm/cpu/armv8/fsl-lsch3
diff options
authorJ. German Rivera <>2014-06-23 15:15:55 -0700
committerAlbert ARIBAUD <>2014-07-03 08:40:58 +0200
commitb940ca64b22ba8980fd4ec8dda028f6b1a2ed79d (patch)
treeb10ed6b9111d3a6522957b1a85eed5492f09f65a /arch/arm/cpu/armv8/fsl-lsch3
parent2f78eae5064728d6cd907148cfeaf8ba3e63b0ef (diff)
armv8/fsl-lsch3: Add support to load and start MC Firmware
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <> Signed-off-by: York Sun <> Signed-off-by: Lijun Pan <> Signed-off-by: Shruti Kanetkar <>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3')
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 46965f08ad..c129d032f4 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -12,6 +12,7 @@
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include "cpu.h"
#include "speed.h"
+#include <fsl_mc.h>
@@ -423,3 +424,13 @@ int print_cpuinfo(void)
return 0;
+int cpu_eth_init(bd_t *bis)
+ int error = 0;
+ error = mc_init(bis);
+ return error;
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