path: root/arch/arm/cpu/armv8/fsl-lsch3
diff options
authorScott Wood <>2015-03-24 13:25:02 -0700
committerYork Sun <>2015-04-23 16:46:50 -0700
commitb2d5ac59859fa946e47fb6ab1f4f3486d4988680 (patch)
tree6c148fbcd0a66138d4d98dcf050df44d24fbef06 /arch/arm/cpu/armv8/fsl-lsch3
parent39b0bbbb23076a7109eeb20b6ae812edcd60ffc2 (diff)
armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3')
2 files changed, 86 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index 4f36e2a605..15a1549e56 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -95,3 +95,41 @@ mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
mcmemsize: MC DRAM block size. If this variable is not defined, the value
+Booting from NAND
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands for QDS which uses
+NAND device with 2KB/page, block size 128KB.
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+SRC should match the cfg_rcw_src, the reset config pins. It depends
+ on the NAND device. See reference manual for cfg_rcw_src.
+SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
+ the example above, 128KB. For easy maintenance, we put it at
+ the beginning of next block from RCW.
+DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE is the size to be copied by PBI.
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+nand write <rcw image in memory> 0 <size of rcw image>
+To form the NAND image, build u-boot with NAND config, for example,
+ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
+nand write <u-boot image in memory> 200000 <size of u-boot image>
+With these two images in NAND device, the board can boot from NAND.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
index 17700ef94e..ca00108e40 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -6,8 +6,13 @@
#include <common.h>
#include <fsl_ifc.h>
+#include <nand.h>
+#include <spl.h>
#include <asm/arch-fsl-lsch3/soc.h>
#include <asm/io.h>
+#include <asm/global_data.h>
static void erratum_a008751(void)
@@ -18,8 +23,51 @@ static void erratum_a008751(void)
+static void erratum_rcw_src(void)
+#if defined(CONFIG_SPL)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+ u32 val;
+ val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+ val &= ~DCFG_PORSR1_RCW_SRC;
+ out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
void fsl_lsch3_early_init_f(void)
+ erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
+void board_init_f(ulong dummy)
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+ arch_cpu_init();
+ board_early_init_f();
+ timer_init();
+ env_init();
+ gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+ serial_init();
+ console_init_f();
+ dram_init();
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+ board_init_r(NULL, 0);
+u32 spl_boot_device(void)
OpenPOWER on IntegriCloud