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| author | York Sun <yorksun@freescale.com> | 2014-02-26 13:26:02 -0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-07 17:43:32 +0200 |
| commit | f5222cfd49bd3681008039e82aa7a1db3e6c9af4 (patch) | |
| tree | f7f81d3f14300d54b4f12125a56b8ce7f17339d4 /arch/arm/cpu/armv8/cache_v8.c | |
| parent | 2c67e0e7cfa750b006725d3a42f42d3926979b90 (diff) | |
| download | talos-obmc-uboot-f5222cfd49bd3681008039e82aa7a1db3e6c9af4.tar.gz talos-obmc-uboot-f5222cfd49bd3681008039e82aa7a1db3e6c9af4.zip | |
armv8/cache: Consolidate setting for MAIR and TCR
Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
Diffstat (limited to 'arch/arm/cpu/armv8/cache_v8.c')
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 131fdaba3f..7acae1b0ac 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -45,15 +45,31 @@ static void mmu_setup(void) /* load TTBR0 */ el = current_el(); - if (el == 1) + if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else if (el == 2) + asm volatile("msr tcr_el1, %0" + : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) + : "memory"); + asm volatile("msr mair_el1, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else if (el == 2) { asm volatile("msr ttbr0_el2, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else + asm volatile("msr tcr_el2, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el2, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else { asm volatile("msr ttbr0_el3, %0" : : "r" (gd->arch.tlb_addr) : "memory"); + asm volatile("msr tcr_el3, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el3, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); |
