diff options
| author | Mathieu J. Poirier <mathieu.poirier@linaro.org> | 2012-07-31 08:59:25 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:19 +0200 |
| commit | 9652de7c488c4915c91626b71fa553d3ed13da47 (patch) | |
| tree | 7b2df3cf96717fdc8c2938bb228b683f9a8f9136 /arch/arm/cpu/armv7/u8500/prcmu.c | |
| parent | 42cb8fb6cb2c869229b0158e3c86c50fb242d6aa (diff) | |
| download | talos-obmc-uboot-9652de7c488c4915c91626b71fa553d3ed13da47.tar.gz talos-obmc-uboot-9652de7c488c4915c91626b71fa553d3ed13da47.zip | |
snowball: Adding architecture dependent initialisation
Enabling timers and clocks in PRCMU and cleaning up mailbox.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch/arm/cpu/armv7/u8500/prcmu.c')
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/prcmu.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index b256d27b84..4918bbc1ca 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -40,6 +40,8 @@ #define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) #define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) +#define I2C_MBOX_BIT (1 << 5) + static int prcmu_is_ready(void) { int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; @@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) return -1; } } + +void u8500_prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); + + /* Clean up the mailbox interrupts after pre-u-boot code. */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); +} |
