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| author | Nishanth Menon <nm@ti.com> | 2015-08-13 09:51:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-28 12:33:13 -0400 |
| commit | 76cff2b10857c86211ef60024e672ce178cb6d69 (patch) | |
| tree | fdf9d2554b43cbcd5e08c0c0e51b2344a8224896 /arch/arm/cpu/armv7/omap5 | |
| parent | 03589234090db645f80896a2ee5bce98096172da (diff) | |
| download | talos-obmc-uboot-76cff2b10857c86211ef60024e672ce178cb6d69.tar.gz talos-obmc-uboot-76cff2b10857c86211ef60024e672ce178cb6d69.zip | |
ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index d01ce88306..fffe0ee913 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -11,6 +11,7 @@ */ #include <asm/omap_common.h> +#include <asm/io.h> struct prcm_regs const omap5_es1_prcm = { /* cm1.ckgen */ @@ -379,6 +380,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .ctrl_core_sma_sw_0 = 0x4A0023FC, + .ctrl_core_sma_sw_1 = 0x4A002534, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -994,3 +996,10 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3main1_tptc1_clkctrl = 0x4a008778, .cm_l3main1_tptc2_clkctrl = 0x4a008780, }; + +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits) +{ + u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 : + (*ctrl)->ctrl_core_sma_sw_0; + clrsetbits_le32(reg, clear_bits, set_bits); +} |
