diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2015-02-23 18:39:44 +0530 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-04-14 05:48:08 +0200 |
| commit | d3cfcb3e2cf44ab7493c9ca0b7a6368bdf3df2d0 (patch) | |
| tree | 8763fdd7809382517a90dd13141ddd07806e5a6f /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | 5877de916510cc2030eafe3761a835726956c7d3 (diff) | |
| download | talos-obmc-uboot-d3cfcb3e2cf44ab7493c9ca0b7a6368bdf3df2d0.tar.gz talos-obmc-uboot-d3cfcb3e2cf44ab7493c9ca0b7a6368bdf3df2d0.zip | |
ARM: DRA7: Enable clocks for USB OTGSS and USB PHY
Enabled clocks for dwc3 controller and USB PHY present in DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index b9734fea8f..e4abb25fc2 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -460,6 +460,10 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, +#ifdef CONFIG_USB_DWC3 + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, +#endif 0 }; @@ -491,6 +495,16 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); +#ifdef CONFIG_USB_DWC3 + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); +#endif + /* Set the correct clock dividers for mmc */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK); |
