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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-02-12 01:33:43 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:10 -0400 |
| commit | 47abc3df701d8bc26f311350aa523fc1d0f8ad4e (patch) | |
| tree | 057c11204cfdc270720f49af35258b2708caa6e4 /arch/arm/cpu/armv7/omap-common | |
| parent | afc2f9dcf1a4a478e51a84b1a162bca19c7b7715 (diff) | |
| download | talos-obmc-uboot-47abc3df701d8bc26f311350aa523fc1d0f8ad4e.tar.gz talos-obmc-uboot-47abc3df701d8bc26f311350aa523fc1d0f8ad4e.zip | |
ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.
While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x
Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/clocks-common.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336850..818a96337e 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h21 >= 0) + writel(params->h21, &dpll_regs->cm_div_h21_dpll); if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll); + if (params->h24 >= 0) + writel(params->h24, &dpll_regs->cm_div_h24_dpll); } static inline void do_bypass_dpll(u32 const base) @@ -319,11 +323,6 @@ void configure_mpu_dpll(void) CM_CLKSEL_DCC_EN_MASK); } - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - params = get_mpu_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); |
