Merge branch 'master' of git://git.denx.de/u-boot-arm

7 files changed, 226 insertions, 57 deletions

diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 6a3a1bb354..47f24f580e 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 
-ALL-y	+= $(obj)u-boot.imx
+ALL-y	+= $(OBJTREE)/u-boot.imx
 
 endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 4ff19c37ef..00b9aba457 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 clock setup code
+ * Freescale i.MX23/i.MX28 clock setup code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -32,16 +32,25 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 
-/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+/*
+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
+ *   iMX23: datasheet section 4.2
+ *   iMX28: datasheet section 10.2
+ */
 #define	PLL_FREQ_KHZ	480000
 #define	PLL_FREQ_COEF	18
-/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
 #define	XTAL_FREQ_KHZ	24000
 
 #define	PLL_FREQ_MHZ	(PLL_FREQ_KHZ / 1000)
 #define	XTAL_FREQ_MHZ	(XTAL_FREQ_KHZ / 1000)
 
-static uint32_t mx28_get_pclk(void)
+#if defined(CONFIG_MX23)
+#define MXC_SSPCLK_MAX MXC_SSPCLK0
+#elif defined(CONFIG_MX28)
+#define MXC_SSPCLK_MAX MXC_SSPCLK3
+#endif
+
+static uint32_t mxs_get_pclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -73,7 +82,7 @@ static uint32_t mx28_get_pclk(void)
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
 
-static uint32_t mx28_get_hclk(void)
+static uint32_t mxs_get_hclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -88,10 +97,10 @@ static uint32_t mx28_get_hclk(void)
 		return 0;
 
 	div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
-	return mx28_get_pclk() / div;
+	return mxs_get_pclk() / div;
 }
 
-static uint32_t mx28_get_emiclk(void)
+static uint32_t mxs_get_emiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -116,11 +125,17 @@ static uint32_t mx28_get_emiclk(void)
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
 
-static uint32_t mx28_get_gpmiclk(void)
+static uint32_t mxs_get_gpmiclk(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
+#if defined(CONFIG_MX23)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
+#elif defined(CONFIG_MX28)
+	uint8_t *reg =
+		&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
+#endif
 	uint32_t clkctrl, clkseq, div;
 	uint8_t clkfrac, frac;
 
@@ -134,7 +149,7 @@ static uint32_t mx28_get_gpmiclk(void)
 	}
 
 	/* REF Path */
-	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	clkfrac = readb(reg);
 	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@@ -143,7 +158,7 @@ static uint32_t mx28_get_gpmiclk(void)
 /*
  * Set IO clock frequency, in kHz
  */
-void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -176,7 +191,7 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 /*
  * Get IO clock, returns IO clock in kHz
  */
-static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
+static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -197,13 +212,13 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 /*
  * Configure SSP clock frequency, in kHz
  */
-void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clk, clkreg;
 
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@@ -216,7 +231,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 	if (xtal)
 		clk = XTAL_FREQ_KHZ;
 	else
-		clk = mx28_get_ioclk(ssp >> 1);
+		clk = mxs_get_ioclk(ssp >> 1);
 
 	if (freq > clk)
 		return;
@@ -241,14 +256,14 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 /*
  * Return SSP frequency, in kHz
  */
-static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
+static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t clkreg;
 	uint32_t clk, tmp;
 
-	if (ssp > MXC_SSPCLK3)
+	if (ssp > MXC_SSPCLK_MAX)
 		return 0;
 
 	tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
@@ -263,7 +278,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 	if (tmp == 0)
 		return 0;
 
-	clk = mx28_get_ioclk(ssp >> 1);
+	clk = mxs_get_ioclk(ssp >> 1);
 
 	return clk / tmp;
 }
@@ -271,14 +286,14 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 /*
  * Set SSP/MMC bus frequency, in kHz)
  */
-void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
 	struct mxs_ssp_regs *ssp_regs;
-	const uint32_t sspclk = mx28_get_sspclk(bus);
+	const uint32_t sspclk = mxs_get_sspclk(bus);
 	uint32_t reg;
 	uint32_t divide, rate, tgtclk;
 
-	ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+	ssp_regs = mxs_ssp_regs_by_bus(bus);
 
 	/*
 	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
@@ -313,28 +328,30 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_ARM_CLK:
-		return mx28_get_pclk() * 1000000;
+		return mxs_get_pclk() * 1000000;
 	case MXC_GPMI_CLK:
-		return mx28_get_gpmiclk() * 1000000;
+		return mxs_get_gpmiclk() * 1000000;
 	case MXC_AHB_CLK:
 	case MXC_IPG_CLK:
-		return mx28_get_hclk() * 1000000;
+		return mxs_get_hclk() * 1000000;
 	case MXC_EMI_CLK:
-		return mx28_get_emiclk();
+		return mxs_get_emiclk();
 	case MXC_IO0_CLK:
-		return mx28_get_ioclk(MXC_IOCLK0);
+		return mxs_get_ioclk(MXC_IOCLK0);
 	case MXC_IO1_CLK:
-		return mx28_get_ioclk(MXC_IOCLK1);
+		return mxs_get_ioclk(MXC_IOCLK1);
+	case MXC_XTAL_CLK:
+		return XTAL_FREQ_KHZ * 1000;
 	case MXC_SSP0_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK0);
+		return mxs_get_sspclk(MXC_SSPCLK0);
+#ifdef CONFIG_MX28
 	case MXC_SSP1_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK1);
+		return mxs_get_sspclk(MXC_SSPCLK1);
 	case MXC_SSP2_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK2);
+		return mxs_get_sspclk(MXC_SSPCLK2);
 	case MXC_SSP3_CLK:
-		return mx28_get_sspclk(MXC_SSPCLK3);
-	case MXC_XTAL_CLK:
-		return XTAL_FREQ_KHZ * 1000;
+		return mxs_get_sspclk(MXC_SSPCLK3);
+#endif
 	}
 
 	return 0;
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 6ce8019b83..e2b41965db 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -1,5 +1,5 @@
 /*
- * Freescale i.MX28 common code
+ * Freescale i.MX23/i.MX28 common code
  *
  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  * on behalf of DENX Software Engineering GmbH
@@ -35,6 +35,7 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -196,6 +197,8 @@ static const char *get_cpu_type(void)
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		return "23";
 	case HW_DIGCTL_CHIPID_MX28:
 		return "28";
 	default:
@@ -210,6 +213,21 @@ static const char *get_cpu_rev(void)
 	uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
 
 	switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+	case HW_DIGCTL_CHIPID_MX23:
+		switch (rev) {
+		case 0x0:
+			return "1.0";
+		case 0x1:
+			return "1.1";
+		case 0x2:
+			return "1.2";
+		case 0x3:
+			return "1.3";
+		case 0x4:
+			return "1.4";
+		default:
+			return "??";
+		}
 	case HW_DIGCTL_CHIPID_MX28:
 		switch (rev) {
 		case 0x1:
@@ -276,7 +294,7 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
-static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
+__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
 {
 	mac[0] = 0x00;
 	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
@@ -285,9 +303,6 @@ static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
 		mac[5] += 1;
 }
 
-void mx28_adjust_mac(int dev_id, unsigned char *mac)
-	__attribute__((weak, alias("__mx28_adjust_mac")));
-
 #ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP
 
 #define	MXS_OCOTP_MAX_TIMEOUT	1000000
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 1b8502eb9d..7e7044033e 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -51,12 +51,21 @@ void early_delay(int delay)
 
 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
+	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#elif defined(CONFIG_MX28)
 	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+#endif
 };
 
 static uint8_t mxs_get_bootmode_index(void)
@@ -68,6 +77,21 @@ static uint8_t mxs_get_bootmode_index(void)
 	/* Setup IOMUX of bootmode pads to GPIO */
 	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
 
+#if defined(CONFIG_MX23)
+	/* Setup bootmode pins as GPIO input */
+	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
+	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
+	gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
+	gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
+	gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
+
+	/* Read bootmode pads */
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#elif defined(CONFIG_MX28)
 	/* Setup bootmode pins as GPIO input */
 	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
 	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
@@ -83,6 +107,7 @@ static uint8_t mxs_get_bootmode_index(void)
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
 	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+#endif
 
 	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
 		masked = bootmode & mxs_boot_modes[i].boot_mask;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 401c51362b..f8392f6398 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <linux/compiler.h>
 
 #include "mxs_init.h"
 
@@ -83,16 +84,30 @@ static uint32_t dram_vals[] = {
 	0x06120612, 0x04320432, 0x04320432, 0x00040004,
 	0x00040004, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00010001
+
+/*
+ * i.MX23 DDR at 133MHz
+ */
+#elif defined(CONFIG_MX23)
+	0x01010001, 0x00010100, 0x01000101, 0x00000001,
+	0x00000101, 0x00000000, 0x00010000, 0x01000001,
+	0x00000000, 0x00000001, 0x07000200, 0x00070202,
+	0x02020000, 0x04040a01, 0x00000201, 0x02040000,
+	0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
+	0x02061521, 0x0000000a, 0x00080008, 0x00200020,
+	0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+	0x00000000, 0x00000020, 0x00000020, 0x00c80000,
+	0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
+	0x00000101, 0x00040001, 0x00000000, 0x00000000,
+	0x00010000
 #else
 #error Unsupported memory initialization
 #endif
 };
 
-void __mxs_adjust_memory_params(uint32_t *dram_vals)
+__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
-void mxs_adjust_memory_params(uint32_t *dram_vals)
-	__attribute__((weak, alias("__mxs_adjust_memory_params")));
 
 static void initialize_dram_values(void)
 {
@@ -102,19 +117,30 @@ static void initialize_dram_values(void)
 
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+
+#ifdef CONFIG_MX23
+	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
+#endif
 }
 
 static void mxs_mem_init_clock(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+#if defined(CONFIG_MX23)
+	/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
+	const unsigned char divider = 33;
+#elif defined(CONFIG_MX28)
+	/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
+	const unsigned char divider = 21;
+#endif
 
 	/* Gate EMI clock */
 	writeb(CLKCTRL_FRAC_CLKGATE,
 		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
-	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+	/* Set fractional divider for ref_emi */
+	writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
 		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
 	/* Ungate EMI clock */
@@ -197,10 +223,60 @@ uint32_t mxs_mem_get_size(void)
 	return sz;
 }
 
-void mxs_mem_init(void)
+#ifdef CONFIG_MX23
+static void mx23_mem_setup_vddmem(void)
+{
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+		POWER_VDDMEMCTRL_ENABLE_ILIMIT |
+		POWER_VDDMEMCTRL_ENABLE_LINREG |
+		POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
+		&power_regs->hw_power_vddmemctrl);
+
+	early_delay(10000);
+
+	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+		POWER_VDDMEMCTRL_ENABLE_LINREG,
+		&power_regs->hw_power_vddmemctrl);
+}
+
+static void mx23_mem_init(void)
+{
+	mx23_mem_setup_vddmem();
+
+	/*
+	 * Configure the DRAM registers
+	 */
+
+	/* Clear START and SREFRESH bit from DRAM_CTL8 */
+	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
+
+	initialize_dram_values();
+
+	/* Set START bit in DRAM_CTL16 */
+	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
+
+	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
+	early_delay(20000);
+
+	/* Adjust EMI port priority. */
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+	early_delay(20000);
+
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
+
+	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
+	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
+		;
+}
+#endif
+
+#ifdef CONFIG_MX28
+static void mx28_mem_init(void)
 {
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	struct mxs_pinctrl_regs *pinctrl_regs =
 		(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
@@ -208,16 +284,6 @@ void mxs_mem_init(void)
 	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
 
-	/* Power up PLL0 */
-	writel(CLKCTRL_PLL0CTRL0_POWER,
-		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
-
-	early_delay(11000);
-
-	mxs_mem_init_clock();
-
-	mxs_mem_setup_vdda();
-
 	/*
 	 * Configure the DRAM registers
 	 */
@@ -236,6 +302,22 @@ void mxs_mem_init(void)
 	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
 	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
 		;
+}
+#endif
+
+void mxs_mem_init(void)
+{
+	early_delay(11000);
+
+	mxs_mem_init_clock();
+
+	mxs_mem_setup_vdda();
+
+#if defined(CONFIG_MX23)
+	mx23_mem_init();
+#elif defined(CONFIG_MX28)
+	mx28_mem_init();
+#endif
 
 	early_delay(10000);
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index be44c22976..e9d6302b7a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -881,11 +881,23 @@ static void mxs_setup_batt_detect(void)
 	early_delay(10);
 }
 
+static void mxs_ungate_power(void)
+{
+#ifdef CONFIG_MX23
+	struct mxs_power_regs *power_regs =
+		(struct mxs_power_regs *)MXS_POWER_BASE;
+
+	writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
+#endif
+}
+
 void mxs_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
+	mxs_ungate_power();
+
 	mxs_power_clock2xtal();
 	mxs_power_clear_auto_restart();
 	mxs_power_set_linreg();
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
new file mode 100644
index 0000000000..3a51879d5e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -0,0 +1,18 @@
+options {
+	driveTag = 0x00;
+	flags = 0x01;
+}
+
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+	load u_boot_spl > 0x0000;
+	load ivt (entry = 0x0014) > 0x8000;
+	call 0x8000;
+
+	load u_boot > 0x40000100;
+	call 0x40000100;
+}