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authorAlexey Brodkin <abrodkin@synopsys.com>2015-02-03 13:58:12 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2015-02-09 16:41:20 +0300
commit5ff40f3d4226d45c78f3bb9db276f6685b24a89a (patch)
tree81130e1aa3f26a3f7ee5c66b81acd1fca1bf29f6 /arch/arc
parent812980bdd6c9112014f3946d1cb2728a2121ba34 (diff)
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arc: define and use PTAG AUX regs for MMUv3 only
DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/include/asm/arcregs.h4
-rw-r--r--arch/arc/lib/cache.c6
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 31627e65b9..6a36a81c0f 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -23,7 +23,7 @@
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
#define ARC_AUX_IC_IVIL 0x19
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
@@ -42,7 +42,7 @@
#define ARC_AUX_DC_IVDL 0x4A
#define ARC_AUX_DC_FLSH 0x4B
#define ARC_AUX_DC_FLDL 0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_DC_PTAG 0x5C
#endif
#define ARC_BCR_DC_BUILD 0x72
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index fa19a13b7e..fa2a1e77a2 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -101,7 +101,7 @@ void flush_dcache_all(void)
#ifndef CONFIG_SYS_DCACHE_OFF
static void dcache_flush_line(unsigned addr)
{
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_FLDL, addr);
@@ -115,7 +115,7 @@ static void dcache_flush_line(unsigned addr)
* Invalidate I$ for addresses range just flushed from D$.
* If we try to execute data flushed above it will be valid/correct
*/
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_IC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_IC_IVIL, addr);
@@ -145,7 +145,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_IVDL, addr);
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