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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-03 13:58:13 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-09 16:41:20 +0300 |
| commit | 205e7a7b77726abeff57576e2ecf2c6d4dc07ccf (patch) | |
| tree | 5f3bae0b6a43d741cb1aabf10f541b6ec38b921e /arch/arc | |
| parent | 5ff40f3d4226d45c78f3bb9db276f6685b24a89a (diff) | |
| download | talos-obmc-uboot-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.tar.gz talos-obmc-uboot-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.zip | |
arc: select cache settings via menuconfig
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/Kconfig | 19 | ||||
| -rw-r--r-- | arch/arc/include/asm/cache.h | 13 | ||||
| -rw-r--r-- | arch/arc/lib/cache.c | 1 |
3 files changed, 25 insertions, 8 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index f7d2964144..397b179198 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -47,6 +47,25 @@ config ARC_MMU_V3 endchoice +config SYS_ICACHE_OFF + bool "Do not use Instruction Cache" + default n + +config SYS_DCACHE_OFF + bool "Do not use Data Cache" + default n + +config ARC_CACHE_LINE_SHIFT + int "Cache Line Length (as power of 2)" + range 5 7 + default "6" + depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF + help + Starting with ARC700 4.9, Cache line length is configurable, + This option specifies "N", with Line-len = 2 power N + So line lengths of 32, 64, 128 are specified by 5,6,7, respectively + Linux only supports same line lengths for I and D caches. + choice prompt "Target select" diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 368d1f016e..2725961221 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,15 +9,12 @@ #include <config.h> -/* - * The current upper bound for ARC L1 data cache line sizes is 128 bytes. - * We use that value for aligning DMA buffers unless the board config has - * specified an alternate cache line size. - */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#ifdef CONFIG_ARC_CACHE_LINE_SHIFT +#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else -#define ARCH_DMA_MINALIGN 128 +/* Satisfy users of ARCH_DMA_MINALIGN */ +#define ARCH_DMA_MINALIGN 128 #endif #if defined(CONFIG_ARC_MMU_V2) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index fa2a1e77a2..a2277231ba 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -6,6 +6,7 @@ #include <config.h> #include <asm/arcregs.h> +#include <asm/cache.h> /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE (1 << 0) |
