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authorAlexey Brodkin <abrodkin@synopsys.com>2015-03-27 12:47:29 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2015-04-03 09:47:49 +0300
commitae4a351ad9e3b800e8eb55b27c302d8be256540e (patch)
treebf2c39420dd77f91f22083bdd912da76cf7e1439 /arch/arc/lib
parent36d68668e33191d55b2a23c9f0ec0c1ffecd6897 (diff)
downloadtalos-obmc-uboot-ae4a351ad9e3b800e8eb55b27c302d8be256540e.tar.gz
talos-obmc-uboot-ae4a351ad9e3b800e8eb55b27c302d8be256540e.zip
arc: cache - build invalidate_icache_all() and invalidate_dcache_all()
always Make both invalidate_icache_all() and invalidate_dcache_all() available even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or CONFIG_SYS_ICACHE_OFF. This is useful because configuration of U-Boot may not match actual hardware features. Real board may have cache(s) but for some reason we may want to run U-Boot with cache(s) disabled (for example if some peripherals work improperly with existing drivers if data cache is enabled). So board may start with cache(s) enabled (that's the case for ARC cores with built-in caches) but early in U-Boot we disable cache(s) and make sure all contents of data cache gets flushed in RAM. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/lib')
-rw-r--r--arch/arc/lib/cache.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index a2277231ba..30f045a864 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -49,10 +49,12 @@ void icache_disable(void)
void invalidate_icache_all(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
/* Any write to IC_IVIC register triggers invalidation of entire I$ */
write_aux_reg(ARC_AUX_IC_IVIC, 1);
-#endif /* CONFIG_SYS_ICACHE_OFF */
}
int dcache_status(void)
@@ -156,10 +158,12 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
void invalidate_dcache_all(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+ /* If no cache in CPU exit immediately */
+ if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+ return;
+
/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
write_aux_reg(ARC_AUX_DC_IVDC, 1);
-#endif /* CONFIG_SYS_DCACHE_OFF */
}
void flush_cache(unsigned long start, unsigned long size)
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