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authorTom Rini <trini@konsulko.com>2015-04-28 07:28:43 -0400
committerTom Rini <trini@konsulko.com>2015-04-28 07:28:43 -0400
commitcc555bd4f40a652471df4a3621d45ee57df0ca11 (patch)
tree6f1f21e7d5cf9cb29d0169aa4377eea9c0981f98 /README
parent86e6f7eaa15f0aca03bb7c961902563348c2dd05 (diff)
parentc650ca7b4c160193791dc7a52381c71c6a29e871 (diff)
downloadtalos-obmc-uboot-cc555bd4f40a652471df4a3621d45ee57df0ca11.zip
talos-obmc-uboot-cc555bd4f40a652471df4a3621d45ee57df0ca11.tar.gz
Merge branch 'master' of git://git.denx.de/u-boot-spi
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diff --git a/README b/README
index a70af98..ee65fdb 100644
--- a/README
+++ b/README
@@ -3096,17 +3096,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
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