|author||Nishanth Menon <firstname.lastname@example.org>||2015-03-09 17:11:59 -0500|
|committer||Tom Rini <email@example.com>||2015-03-13 09:28:29 -0400|
ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <firstname.lastname@example.org> Tested-by: Matt Porter <email@example.com> Reviewed-by: Tom Rini <firstname.lastname@example.org>
Diffstat (limited to 'README')
1 files changed, 5 insertions, 0 deletions
@@ -690,6 +690,11 @@ The following options need to be configured:
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ NOTE: The following can be machine specific errata. These
+ do have ability to provide rudimentary version and machine
+ specific checks, but expect no product checks.
- Tegra SoC options: