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authorHeiko Schocher <hs@denx.de>2014-07-18 06:07:21 +0200
committerStefano Babic <sbabic@denx.de>2014-07-23 12:26:45 +0200
commit562f8df18da62ae02c4ace1e530451fe82c3312d (patch)
treef3ac604fb5cc1a3865a91a99763f3d855c19bd4f /README
parenta0ae0091d783b1140f8d321d8c6d221aeb0d39d0 (diff)
downloadtalos-obmc-uboot-562f8df18da62ae02c4ace1e530451fe82c3312d.tar.gz
talos-obmc-uboot-562f8df18da62ae02c4ace1e530451fe82c3312d.zip
spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'README')
-rw-r--r--README11
1 files changed, 11 insertions, 0 deletions
diff --git a/README b/README
index a35b92c889..37e4d1b09d 100644
--- a/README
+++ b/README
@@ -2930,6 +2930,17 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
currently Xilinx Zynq qspi support these type of connections.
+ CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+ enable the W#/Vpp signal to disable writing to the status
+ register on ST MICRON flashes like the N25Q128.
+ The status register write enable/disable bit, combined with
+ the W#/VPP signal provides hardware data protection for the
+ device as follows: When the enable/disable bit is set to 1,
+ and the W#/VPP signal is driven LOW, the status register
+ nonvolatile bits become read-only and the WRITE STATUS REGISTER
+ operation will not execute. The only way to exit this
+ hardware-protected mode is to drive W#/VPP HIGH.
+
- SystemACE Support:
CONFIG_SYSTEMACE
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